From db87924fbf64b1e2066f04451d4598fee2534ccf Mon Sep 17 00:00:00 2001 From: Rimas Avizienis Date: Mon, 14 Nov 2011 14:35:10 -0800 Subject: [PATCH] made eret instruction take an illegal inst exception when ET is set --- rocket/src/main/scala/consts.scala | 7 ++++--- rocket/src/main/scala/ctrl.scala | 5 +++-- rocket/src/main/scala/dpath_util.scala | 8 +++++--- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 9c3fece3..d27d1003 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -155,8 +155,8 @@ object Constants val PCR_COMPARE = UFix( 5, 5); val PCR_CAUSE = UFix( 6, 5); val PCR_PTBR = UFix( 7, 5); - val PCR_SENDIPI = UFix( 8, 5); - val PCR_CLEARIPI = UFix( 9, 5); + val PCR_SEND_IPI = UFix( 8, 5); + val PCR_CLR_IPI = UFix( 9, 5); val PCR_COREID = UFix(10, 5); val PCR_K0 = UFix(12, 5); val PCR_K1 = UFix(13, 5); @@ -169,6 +169,7 @@ object Constants val SR_ET = 0; // enable traps val SR_EF = 1; // enable floating point val SR_EV = 2; // enable vector unit + val SR_EC = 3; // enable compressed instruction encoding val SR_PS = 4; // mode stack bit val SR_S = 5; // user/supervisor mode val SR_UX = 6; // 64 bit user mode @@ -176,7 +177,6 @@ object Constants val SR_VM = 16; // VM enable val COREID = 0; - val NUMCORES = 1; val PADDR_BITS = 40; val VADDR_BITS = 43; val PGIDX_BITS = 13; @@ -195,6 +195,7 @@ object Constants val START_ADDR = 0x2000; + val HAVE_RVC = Bool(false); val HAVE_FPU = Bool(false); val HAVE_VEC = Bool(false); } diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index d8628f63..9ee4c92d 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -363,7 +363,8 @@ class rocketCtrl extends Component } } - val illegal_inst = !id_int_val.toBool && !id_fp_val.toBool; + // executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim) + val illegal_inst = !(id_int_val.toBool || id_fp_val.toBool) || (id_eret.toBool && io.dpath.status(SR_ET).toBool); when (reset.toBool || io.dpath.killd) { ex_reg_br_type <== BR_N; @@ -399,7 +400,7 @@ class rocketCtrl extends Component ex_reg_xcpt_ma_inst <== id_reg_xcpt_ma_inst; ex_reg_xcpt_itlb <== id_reg_xcpt_itlb; ex_reg_xcpt_illegal <== illegal_inst; - ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(5)).toBool; + ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool; ex_reg_xcpt_fpu <== id_fp_val.toBool; ex_reg_xcpt_syscall <== id_syscall.toBool; } diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index edbb22af..2d4f6604 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -81,6 +81,7 @@ class rocketDpathPCR extends Component val reg_status_im = Reg(resetVal = Bits(0,8)); val reg_status_sx = Reg(resetVal = Bool(true)); val reg_status_ux = Reg(resetVal = Bool(true)); + val reg_status_ec = Reg(resetVal = Bool(false)); val reg_status_ef = Reg(resetVal = Bool(false)); val reg_status_ev = Reg(resetVal = Bool(false)); val reg_status_s = Reg(resetVal = Bool(true)); @@ -90,7 +91,7 @@ class rocketDpathPCR extends Component val r_irq_timer = Reg(resetVal = Bool(false)); val r_irq_ipi = Reg(resetVal = Bool(false)); - val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, Bits(0,1), reg_status_ev, reg_status_ef, reg_status_et); + val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et); val rdata = Wire() { Bits() }; io.ptbr_wen := reg_status_vm.toBool && !io.exception && io.w.en && (io.w.addr === PCR_PTBR); @@ -151,6 +152,7 @@ class rocketDpathPCR extends Component reg_status_ps <== io.w.data(SR_PS).toBool; reg_status_ev <== HAVE_VEC && io.w.data(SR_EV).toBool; reg_status_ef <== HAVE_FPU && io.w.data(SR_EF).toBool; + reg_status_ec <== HAVE_RVC && io.w.data(SR_EC).toBool; reg_status_et <== io.w.data(SR_ET).toBool; } when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS-1,0).toUFix; } @@ -160,8 +162,8 @@ class rocketDpathPCR extends Component when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(31,0).toUFix; r_irq_timer <== Bool(false); } when (io.w.addr === PCR_CAUSE) { reg_cause <== io.w.data(4,0); } when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data(31,0); } - when (io.w.addr === PCR_SENDIPI) { r_irq_ipi <== Bool(true); } - when (io.w.addr === PCR_CLEARIPI) { r_irq_ipi <== Bool(false); } + when (io.w.addr === PCR_SEND_IPI) { r_irq_ipi <== Bool(true); } + when (io.w.addr === PCR_CLR_IPI) { r_irq_ipi <== Bool(false); } when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; } when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; } when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }