riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

axi4: Deinterleaver must gather R also for single ID

Browse Source 
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
This commit is contained in:
Wesley W. Terpstra 2017-05-08 00:07:45 -07:00
parent 8fc27b0bf2
commit db76ff2d86
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/uncore/axi4/Deinterleaver.scala
View File

@ -38,8 +38,8 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
out.w <> in.w
in.b <> out.b
if (queues == 1) {
// Gracefully do nothing
if (beats <= 1) {
// Nothing to do if only single-beat R
in.r <> out.r
} else {
// Buffer R response
@ -48,7 +48,7 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
// Which ID is being enqueued and dequeued?
val locked = RegInit(Bool(false))
val deq_id = Reg(UInt(width=log2Ceil(queues)))
val deq_id = Reg(UInt(width=log2Up(queues)))
val enq_id = out.r.bits.id
val deq_OH = UIntToOH(deq_id, queues)
val enq_OH = UIntToOH(enq_id, queues)