From db76ff2d8689f96ba344106d3f07915755f4305b Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 8 May 2017 00:07:45 -0700 Subject: [PATCH] axi4: Deinterleaver must gather R also for single ID In order to guarantee that a complete R can be sent without sinking B, the Deinterleaver must do its job even on AXI-Lite. --- src/main/scala/uncore/axi4/Deinterleaver.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/axi4/Deinterleaver.scala b/src/main/scala/uncore/axi4/Deinterleaver.scala index bc926c69..dcdf68b4 100644 --- a/src/main/scala/uncore/axi4/Deinterleaver.scala +++ b/src/main/scala/uncore/axi4/Deinterleaver.scala @@ -38,8 +38,8 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM out.w <> in.w in.b <> out.b - if (queues == 1) { - // Gracefully do nothing + if (beats <= 1) { + // Nothing to do if only single-beat R in.r <> out.r } else { // Buffer R response @@ -48,7 +48,7 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM // Which ID is being enqueued and dequeued? val locked = RegInit(Bool(false)) - val deq_id = Reg(UInt(width=log2Ceil(queues))) + val deq_id = Reg(UInt(width=log2Up(queues))) val enq_id = out.r.bits.id val deq_OH = UIntToOH(deq_id, queues) val enq_OH = UIntToOH(enq_id, queues)