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axi4: Deinterleaver must gather R also for single ID

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In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
This commit is contained in:
Wesley W. Terpstra 2017-05-08 00:07:45 -07:00
parent 8fc27b0bf2
commit db76ff2d86
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/uncore/axi4/Deinterleaver.scala
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@ -38,8 +38,8 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
out.w <> in.w out.w <> in.w
in.b <> out.b in.b <> out.b
if (queues == 1) { if (beats <= 1) {
// Gracefully do nothing // Nothing to do if only single-beat R
in.r <> out.r in.r <> out.r
} else { } else {
// Buffer R response // Buffer R response
@ -48,7 +48,7 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
// Which ID is being enqueued and dequeued? // Which ID is being enqueued and dequeued?
val locked = RegInit(Bool(false)) val locked = RegInit(Bool(false))
val deq_id = Reg(UInt(width=log2Ceil(queues))) val deq_id = Reg(UInt(width=log2Up(queues)))
val enq_id = out.r.bits.id val enq_id = out.r.bits.id
val deq_OH = UIntToOH(deq_id, queues) val deq_OH = UIntToOH(deq_id, queues)
val enq_OH = UIntToOH(enq_id, queues) val enq_OH = UIntToOH(enq_id, queues)