Add return address stack
This commit is contained in:
Andrew Waterman
parent
e3b12e0b85
commit
db59fc65ab
@ -5,41 +5,80 @@ import Util._
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import Node._
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import uncore.constants.AddressConstants._
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case class BTBConfig(entries: Int) {
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case class BTBConfig(entries: Int, nras: Int = 0, inOrder: Boolean = true) {
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val matchBits = PGIDX_BITS
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val pages0 = 1 + log2Up(entries) // is this sensible? what about matchBits?
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val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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}
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class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = VADDR_BITS)
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val target = UInt(width = VADDR_BITS)
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val returnAddr = UInt(width = VADDR_BITS)
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val taken = Bool()
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val isCall = Bool()
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val isReturn = Bool()
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val incorrectTarget = Bool()
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override def clone = new BTBUpdate().asInstanceOf[this.type]
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}
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class BTBResp(implicit conf: BTBConfig) extends Bundle {
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val taken = Bool()
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val target = UInt(width = VADDR_BITS)
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val opaque = UInt(width = conf.opaqueBits)
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override def clone = new BTBResp().asInstanceOf[this.type]
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}
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class RAS(implicit conf: BTBConfig) {
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def push(addr: UInt): Unit = {
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when (count < conf.nras-1) { count := count + 1 }
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stack(pos+1) := addr
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pos := pos+1
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}
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def pop: UInt = {
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count := count - 1
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pos := pos - 1
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stack(pos)
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}
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def clear: Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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require(isPow2(conf.nras))
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private val count = Reg(init=UInt(0,log2Up(conf.nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(conf.nras)))
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private val stack = Vec.fill(conf.nras){Reg(UInt())}
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}
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// fully-associative branch target buffer
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class BTB(conf: BTBConfig) extends Module {
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class BTB(implicit conf: BTBConfig) extends Module {
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val io = new Bundle {
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val current_pc = UInt(INPUT, VADDR_BITS)
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val hit = Bool(OUTPUT)
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val target = UInt(OUTPUT, VADDR_BITS)
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val wen = Bool(INPUT)
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val taken = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val correct_pc = UInt(INPUT, VADDR_BITS)
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val correct_target = UInt(INPUT, VADDR_BITS)
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val req = UInt(INPUT, VADDR_BITS)
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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}
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val idxValid = Vec.fill(conf.entries){Reg(init=Bool(false))}
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val idxs = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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val pages = Vec.fill(conf.pages){Reg(UInt(width=VADDR_BITS-conf.matchBits))}
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val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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val useRAS = Vec.fill(conf.entries){Reg(Bool())}
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private def page(addr: UInt) = addr >> conf.matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid.toBits
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}
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private def tagMatch(addr: UInt): UInt = tagMatch(addr, pageMatch(addr))
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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val idx = addr(conf.matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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@ -47,13 +86,19 @@ class BTB(conf: BTBConfig) extends Module {
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idxValid.toBits & idxMatch & idxPageMatch
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}
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val hits = tagMatch(io.current_pc)
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val idxPageMatch = pageMatch(io.correct_pc)
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val tgtPageMatch = pageMatch(io.correct_target)
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val updates = tagMatch(io.correct_pc, idxPageMatch)
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val anyUpdates = updates.orR
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val update = Pipe(io.update)
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val update_target = io.req
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private var lfsr = LFSR16(io.wen)
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val pageHit = pageMatch(io.req)
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val hits = tagMatch(io.req, pageHit)
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val updatePageHit = pageMatch(update.bits.pc)
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val updateHits = tagMatch(update.bits.pc, updatePageHit)
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val taken = update.bits.incorrectTarget || update.bits.taken
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val predicted_taken = update.bits.prediction.valid && update.bits.prediction.bits.taken
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val correction = update.bits.incorrectTarget || update.bits.taken != predicted_taken
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private var lfsr = LFSR16(update.valid)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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@ -62,32 +107,35 @@ class BTB(conf: BTBConfig) extends Module {
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Mux(!valid.andR, PriorityEncoderOH(~valid), rand(valid.getWidth))
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val idxRepl = randOrInvalid(idxValid.toBits)
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val idxWen = updates.toBits | idxRepl & ~anyUpdates.toSInt
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val idxWen =
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if (conf.inOrder) Mux(update.bits.prediction.valid, UIntToOH(update.bits.prediction.bits.opaque), idxRepl)
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else updateHits | Mux(updateHits.orR, UInt(0), idxRepl)
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val useIdxPageMatch = idxPageMatch.orR
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val doIdxPageRepl = !useIdxPageMatch && io.taken
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = !useUpdatePageHit && update.valid
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val idxPageRepl = rand(conf.pages)
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val idxPageUpdate = Mux(useIdxPageMatch, idxPageMatch, idxPageRepl)
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val idxPageUpdate = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(io.correct_pc) === page(io.correct_target)
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val useTgtPageMatch = (tgtPageMatch & ~idxPageReplEn).orR
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val doTgtPageRepl = !useTgtPageMatch && io.taken && !samePage
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val samePage = page(update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = !usePageHit && !samePage && update.valid
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val tgtPageRepl = Mux(samePage, idxPageUpdate, idxPageUpdate(conf.pages-2,0) << 1 | idxPageUpdate(conf.pages-1))
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val tgtPageUpdate = Mux(useTgtPageMatch, tgtPageMatch, tgtPageRepl)
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val tgtPageUpdate = Mux(usePageHit, pageHit, tgtPageRepl)
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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when (io.wen) {
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when (update.valid) {
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for (i <- 0 until conf.entries) {
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when (idxWen(i)) {
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idxValid(i) := io.taken
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when (io.taken) {
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idxs(i) := io.correct_pc
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idxValid(i) := taken
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when (correction) {
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idxs(i) := update.bits.pc
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idxPages(i) := OHToUInt(idxPageUpdate)
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tgts(i) := io.correct_target
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tgts(i) := update_target
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tgtPages(i) := OHToUInt(tgtPageUpdate)
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useRAS(i) := update.bits.isReturn
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}
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}.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
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idxValid(i) := false
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@ -106,9 +154,9 @@ class BTB(conf: BTBConfig) extends Module {
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}
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}
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(io.correct_pc), page(io.correct_target)))
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Mux(idxWritesEven, page(update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(io.correct_target), page(io.correct_pc)))
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Mux(idxWritesEven, page(update_target), page(update.bits.pc)))
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}
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when (io.invalidate) {
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@ -116,6 +164,19 @@ class BTB(conf: BTBConfig) extends Module {
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pageValid.foreach(_ := false)
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}
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io.hit := hits.toBits.orR
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io.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.valid := hits.toBits.orR
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.opaque := OHToUInt(hits)
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if (conf.nras > 0) {
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val ras = new RAS
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when (!ras.isEmpty && Mux1H(hits, useRAS)) {
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io.resp.bits.target := ras.pop
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}
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when (io.update.valid && io.update.bits.isCall) {
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ras.push(io.update.bits.returnAddr)
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}
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when (io.invalidate) { ras.clear }
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}
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}
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@ -53,6 +53,7 @@ class CtrlDpathIO(implicit conf: RocketConfiguration) extends Bundle
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val ll_wen = Bool(INPUT)
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val ll_waddr = UInt(INPUT, 5)
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val ex_waddr = UInt(INPUT, 5)
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val ex_rs = Vec.fill(2)(UInt(INPUT, 5))
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val mem_waddr = UInt(INPUT, 5)
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val wb_waddr = UInt(INPUT, 5)
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val status = new Status().asInput
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@ -66,15 +67,15 @@ abstract trait DecodeConstants
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val xpr64 = Y
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val decode_default =
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// fence.i
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// jalr mul_val | sret
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// fp_val | renx2 | div_val | | syscall
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// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
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// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | fence
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// | | | | | | | | | | | | | | | | | | | | | | | | amo
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// | | | | | | | | | | | | | | | | | | | | | | | | |
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List(N, X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X)
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// fence.i
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// jalr mul_val | sret
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// fp_val | renx2 | div_val | | syscall
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// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
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// val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
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// | | | | brtype | | | | | | | | | | | | | | | | | | | fence
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// | | | | | | | | | | | | | | | | | | | | | | | | | amo
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// | | | | | | | | | | | | | | | | | | | | | | | | | |
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List(N, X,X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X)
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val table: Array[(UInt, List[UInt])]
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}
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@ -82,225 +83,225 @@ abstract trait DecodeConstants
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object XDecode extends DecodeConstants
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{
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val table = Array(
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// fence.i
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// jalr mul_val | sret
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// fp_val | renx2 | div_val | | syscall
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// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
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// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | fence
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// | | | | | | | | | | | | | | | | | | | | | | | | amo
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// | | | | | | | | | | | | | | | | | | | | | | | | |
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BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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// fence.i
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// jalr mul_val | sret
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// fp_val | renx2 | div_val | | syscall
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// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
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// val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
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// | | | | brtype | | | | | | | | | | | | | | | | | | | fence
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// | | | | | | | | | | | | | | | | | | | | | | | | | amo
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// | | | | | | | | | | | | | | | | | | | | | | | | | |
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BNE-> List(Y, N,N,Y,BR_NE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BEQ-> List(Y, N,N,Y,BR_EQ, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BLT-> List(Y, N,N,Y,BR_LT, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BLTU-> List(Y, N,N,Y,BR_LTU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BGE-> List(Y, N,N,Y,BR_GE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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BGEU-> List(Y, N,N,Y,BR_GEU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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JAL-> List(Y, N,N,Y,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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JALR-> List(Y, N,N,N,BR_X, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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AUIPC-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N),
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LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N),
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LW-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N),
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LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N),
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LBU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N),
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LHU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N),
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LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N),
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SB-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N),
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SH-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
SW-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
LB-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LH-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LW-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LD-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LBU-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LHU-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LWU-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SB-> List(Y, N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
SH-> List(Y, N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
SW-> List(Y, N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
SD-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
|
||||
AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOXOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOXOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOADD_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOXOR_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOSWAP_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOAND_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOOR_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMIN_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMINU_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAX_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAXU_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOADD_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOSWAP_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOXOR_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOAND_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOOR_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMIN_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMINU_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAX_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
AMOMAXU_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
|
||||
LR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
LR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
SC_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
SC_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
LR_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
LR_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
SC_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
SC_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
|
||||
|
||||
LUI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
XORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
AND-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
OR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
XOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
LUI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADDI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLTI -> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLTIU-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ANDI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ORI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
XORI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLLI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRLI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRAI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADD-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SUB-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLT-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLTU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
AND-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
OR-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
XOR-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLL-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRL-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRA-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
|
||||
ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADDIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLLIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRLIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRAIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
ADDW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SUBW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SLLW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRLW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
SRAW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
|
||||
MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MUL-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULH-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULHU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULHSU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
MULW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
|
||||
DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIV-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIVU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REM-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REMU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIVW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
DIVUW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REMW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
REMUW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
|
||||
|
||||
SCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N),
|
||||
SRET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N),
|
||||
FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N),
|
||||
FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N),
|
||||
CSRRW-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
|
||||
CSRRS-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
|
||||
CSRRC-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N),
|
||||
CSRRWI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
|
||||
CSRRSI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
|
||||
CSRRCI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N))
|
||||
SCALL-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N),
|
||||
SRET-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N),
|
||||
FENCE-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N),
|
||||
FENCE_I-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N),
|
||||
CSRRW-> List(Y, N,N,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
|
||||
CSRRS-> List(Y, N,N,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
|
||||
CSRRC-> List(Y, N,N,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N),
|
||||
CSRRWI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
|
||||
CSRRSI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
|
||||
CSRRCI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N))
|
||||
}
|
||||
|
||||
object FDecode extends DecodeConstants
|
||||
{
|
||||
val table = Array(
|
||||
// fence.i
|
||||
// jalr mul_val | sret
|
||||
// fp_val | renx2 | div_val | | syscall
|
||||
// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
|
||||
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | fence
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | amo
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCLASS_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCLASS_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FMV_S_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMV_D_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N))
|
||||
// fence.i
|
||||
// jalr mul_val | sret
|
||||
// fp_val | renx2 | div_val | | syscall
|
||||
// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
|
||||
// val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
|
||||
// | | | | brtype | | | | | | | | | | | | | | | | | | | fence
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | | amo
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
FCVT_S_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJ_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJ_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJX_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJX_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJN_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSGNJN_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMIN_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMIN_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMAX_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMAX_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FADD_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FADD_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSUB_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSUB_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMUL_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMUL_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMADD_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMADD_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMSUB_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMSUB_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMADD_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMADD_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMSUB_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FNMSUB_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCLASS_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCLASS_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FMV_X_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FMV_X_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_W_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_W_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_WU_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_WU_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_L_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_L_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_LU_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_LU_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FEQ_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FEQ_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLT_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLT_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLE_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FLE_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
FMV_S_X-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FMV_D_X-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_W-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_W-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_WU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_WU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_L-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_L-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_S_LU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FCVT_D_LU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FLW-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FLD-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSW-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
FSD-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N))
|
||||
}
|
||||
|
||||
object RoCCDecode extends DecodeConstants
|
||||
{
|
||||
val table = Array(
|
||||
// fence.i
|
||||
// jalr mul_val | sret
|
||||
// fp_val | renx2 | div_val | | syscall
|
||||
// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
|
||||
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | fence
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | amo
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N))
|
||||
// fence.i
|
||||
// jalr mul_val | sret
|
||||
// fp_val | renx2 | div_val | | syscall
|
||||
// | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
|
||||
// val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
|
||||
// | | | | brtype | | | | | | | | | | | | | | | | | | | fence
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | | amo
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
CUSTOM0-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM0_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM1_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM2_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
|
||||
CUSTOM3_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N))
|
||||
}
|
||||
|
||||
class Control(implicit conf: RocketConfiguration) extends Module
|
||||
@ -325,62 +326,65 @@ class Control(implicit conf: RocketConfiguration) extends Module
|
||||
|
||||
val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
|
||||
|
||||
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
|
||||
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: (id_branch: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
|
||||
val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0
|
||||
val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: cs2 = cs1
|
||||
val id_csr :: (id_fence_i: Bool) :: (id_sret: Bool) :: (id_syscall: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2
|
||||
|
||||
val ex_reg_xcpt_interrupt = Reg(init=Bool(false))
|
||||
val ex_reg_valid = Reg(init=Bool(false))
|
||||
val ex_reg_sret = Reg(init=Bool(false))
|
||||
val ex_reg_wen = Reg(init=Bool(false))
|
||||
val ex_reg_fp_wen = Reg(init=Bool(false))
|
||||
val ex_reg_flush_inst = Reg(init=Bool(false))
|
||||
val ex_reg_jalr = Reg(init=Bool(false))
|
||||
val ex_reg_btb_hit = Reg(init=Bool(false))
|
||||
val ex_reg_div_mul_val = Reg(init=Bool(false))
|
||||
val ex_reg_mem_val = Reg(init=Bool(false))
|
||||
val ex_reg_xcpt = Reg(init=Bool(false))
|
||||
val ex_reg_fp_val = Reg(init=Bool(false))
|
||||
val ex_reg_rocc_val = Reg(init=Bool(false))
|
||||
val ex_reg_replay_next = Reg(init=Bool(false))
|
||||
val ex_reg_load_use = Reg(init=Bool(false))
|
||||
val ex_reg_csr = Reg(init=CSR.N)
|
||||
val ex_reg_br_type = Reg(init=BR_N)
|
||||
val ex_reg_xcpt_interrupt = Reg(Bool())
|
||||
val ex_reg_valid = Reg(Bool())
|
||||
val ex_reg_branch = Reg(Bool())
|
||||
val ex_reg_jalr = Reg(Bool())
|
||||
val ex_reg_predicted_taken = Reg(Bool())
|
||||
val ex_reg_btb_hit = Reg(Bool())
|
||||
val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone)
|
||||
val ex_reg_br_type = Reg(UInt())
|
||||
val ex_reg_sret = Reg(Bool())
|
||||
val ex_reg_wen = Reg(Bool())
|
||||
val ex_reg_fp_wen = Reg(Bool())
|
||||
val ex_reg_flush_inst = Reg(Bool())
|
||||
val ex_reg_div_mul_val = Reg(Bool())
|
||||
val ex_reg_mem_val = Reg(Bool())
|
||||
val ex_reg_xcpt = Reg(Bool())
|
||||
val ex_reg_fp_val = Reg(Bool())
|
||||
val ex_reg_rocc_val = Reg(Bool())
|
||||
val ex_reg_replay_next = Reg(Bool())
|
||||
val ex_reg_load_use = Reg(Bool())
|
||||
val ex_reg_csr = Reg(UInt())
|
||||
val ex_reg_mem_cmd = Reg(Bits())
|
||||
val ex_reg_mem_type = Reg(Bits())
|
||||
val ex_reg_cause = Reg(UInt())
|
||||
|
||||
val mem_reg_xcpt_interrupt = Reg(init=Bool(false))
|
||||
val mem_reg_valid = Reg(init=Bool(false))
|
||||
val mem_reg_sret = Reg(init=Bool(false))
|
||||
val mem_reg_wen = Reg(init=Bool(false))
|
||||
val mem_reg_fp_wen = Reg(init=Bool(false))
|
||||
val mem_reg_flush_inst = Reg(init=Bool(false))
|
||||
val mem_reg_div_mul_val = Reg(init=Bool(false))
|
||||
val mem_reg_mem_val = Reg(init=Bool(false))
|
||||
val mem_reg_xcpt = Reg(init=Bool(false))
|
||||
val mem_reg_fp_val = Reg(init=Bool(false))
|
||||
val mem_reg_rocc_val = Reg(init=Bool(false))
|
||||
val mem_reg_replay = Reg(init=Bool(false))
|
||||
val mem_reg_replay_next = Reg(init=Bool(false))
|
||||
val mem_reg_csr = Reg(init=CSR.N)
|
||||
val mem_reg_xcpt_interrupt = Reg(Bool())
|
||||
val mem_reg_valid = Reg(Bool())
|
||||
val mem_reg_sret = Reg(Bool())
|
||||
val mem_reg_wen = Reg(Bool())
|
||||
val mem_reg_fp_wen = Reg(Bool())
|
||||
val mem_reg_flush_inst = Reg(Bool())
|
||||
val mem_reg_div_mul_val = Reg(Bool())
|
||||
val mem_reg_mem_val = Reg(Bool())
|
||||
val mem_reg_xcpt = Reg(Bool())
|
||||
val mem_reg_fp_val = Reg(Bool())
|
||||
val mem_reg_rocc_val = Reg(Bool())
|
||||
val mem_reg_replay = Reg(Bool())
|
||||
val mem_reg_replay_next = Reg(Bool())
|
||||
val mem_reg_csr = Reg(UInt())
|
||||
val mem_reg_cause = Reg(UInt())
|
||||
val mem_reg_slow_bypass = Reg(Bool())
|
||||
|
||||
val wb_reg_valid = Reg(init=Bool(false))
|
||||
val wb_reg_csr = Reg(init=CSR.N)
|
||||
val wb_reg_wen = Reg(init=Bool(false))
|
||||
val wb_reg_fp_wen = Reg(init=Bool(false))
|
||||
val wb_reg_rocc_val = Reg(init=Bool(false))
|
||||
val wb_reg_flush_inst = Reg(init=Bool(false))
|
||||
val wb_reg_mem_val = Reg(init=Bool(false))
|
||||
val wb_reg_sret = Reg(init=Bool(false))
|
||||
val wb_reg_xcpt = Reg(init=Bool(false))
|
||||
val wb_reg_replay = Reg(init=Bool(false))
|
||||
val wb_reg_valid = Reg(Bool())
|
||||
val wb_reg_csr = Reg(UInt())
|
||||
val wb_reg_wen = Reg(Bool())
|
||||
val wb_reg_fp_wen = Reg(Bool())
|
||||
val wb_reg_rocc_val = Reg(Bool())
|
||||
val wb_reg_flush_inst = Reg(Bool())
|
||||
val wb_reg_mem_val = Reg(Bool())
|
||||
val wb_reg_sret = Reg(Bool())
|
||||
val wb_reg_xcpt = Reg(Bool())
|
||||
val wb_reg_replay = Reg(Bool())
|
||||
val wb_reg_cause = Reg(UInt())
|
||||
val wb_reg_fp_val = Reg(init=Bool(false))
|
||||
val wb_reg_div_mul_val = Reg(init=Bool(false))
|
||||
val wb_reg_fp_val = Reg(Bool())
|
||||
val wb_reg_div_mul_val = Reg(Bool())
|
||||
|
||||
val take_pc = Bool()
|
||||
val take_pc_wb = Bool()
|
||||
@ -452,8 +456,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
|
||||
when (id_xcpt) { ex_reg_cause := id_cause }
|
||||
|
||||
when (ctrl_killd) {
|
||||
ex_reg_jalr := Bool(false)
|
||||
ex_reg_btb_hit := Bool(false)
|
||||
ex_reg_branch := false
|
||||
ex_reg_jalr := false
|
||||
ex_reg_predicted_taken := false
|
||||
ex_reg_btb_hit := false
|
||||
ex_reg_div_mul_val := Bool(false)
|
||||
ex_reg_mem_val := Bool(false)
|
||||
ex_reg_valid := Bool(false)
|
||||
@ -466,13 +472,15 @@ class Control(implicit conf: RocketConfiguration) extends Module
|
||||
ex_reg_replay_next := Bool(false)
|
||||
ex_reg_load_use := Bool(false)
|
||||
ex_reg_csr := CSR.N
|
||||
ex_reg_br_type := BR_N
|
||||
ex_reg_xcpt := Bool(false)
|
||||
}
|
||||
.otherwise {
|
||||
ex_reg_br_type := id_br_type
|
||||
ex_reg_jalr := id_jalr
|
||||
ex_reg_btb_hit := io.imem.resp.bits.taken && !id_jalr
|
||||
ex_reg_branch := id_branch
|
||||
ex_reg_jalr := id_jalr
|
||||
ex_reg_predicted_taken := io.imem.btb_resp.valid && io.imem.btb_resp.bits.taken
|
||||
when (id_branch) { ex_reg_br_type := id_br_type }
|
||||
ex_reg_btb_hit := io.imem.btb_resp.valid
|
||||
when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits }
|
||||
ex_reg_div_mul_val := id_mul_val || id_div_val
|
||||
ex_reg_mem_val := id_mem_val.toBool
|
||||
ex_reg_valid := Bool(true)
|
||||
@ -635,8 +643,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
|
||||
Mux(replay_wb, PC_WB, // replay
|
||||
PC_EX)))// branch/jal[r]
|
||||
|
||||
io.imem.req.bits.mispredict := !take_pc_wb && take_pc_ex && !ex_reg_xcpt
|
||||
io.imem.req.bits.taken := !ex_reg_btb_hit || ex_reg_jalr
|
||||
io.imem.btb_update.valid := ex_reg_btb_hit || !take_pc_wb && (ex_reg_branch || ex_reg_jalr) && !ex_reg_xcpt
|
||||
io.imem.btb_update.bits.prediction.valid := ex_reg_btb_hit
|
||||
io.imem.btb_update.bits.prediction.bits := ex_reg_btb_resp
|
||||
io.imem.btb_update.bits.taken := ex_reg_jalr || io.dpath.ex_br_taken ^ io.dpath.ex_predicted_taken
|
||||
io.imem.btb_update.bits.incorrectTarget := ex_reg_jalr && !io.dpath.jalr_eq
|
||||
io.imem.btb_update.bits.isCall := ex_reg_wen && io.dpath.ex_waddr(0)
|
||||
io.imem.btb_update.bits.isReturn := ex_reg_jalr && io.dpath.ex_rs(0) === 1
|
||||
io.imem.req.valid := take_pc
|
||||
|
||||
val bypassDst = Array(id_raddr1, id_raddr2)
|
||||
@ -723,7 +736,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
|
||||
io.dpath.ex_fp_val:= ex_reg_fp_val
|
||||
io.dpath.mem_fp_val:= mem_reg_fp_val
|
||||
io.dpath.ex_jalr := ex_reg_jalr
|
||||
io.dpath.ex_predicted_taken := ex_reg_btb_hit
|
||||
io.dpath.ex_predicted_taken := ex_reg_branch && ex_reg_btb_hit && ex_reg_btb_resp.taken
|
||||
io.dpath.ex_wen := ex_reg_wen
|
||||
io.dpath.mem_wen := mem_reg_wen
|
||||
io.dpath.ll_ready := !wb_reg_wen
|
||||
@ -732,7 +745,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
|
||||
io.dpath.csr := wb_reg_csr
|
||||
io.dpath.sret := wb_reg_sret
|
||||
io.dpath.ex_mem_type := ex_reg_mem_type
|
||||
io.dpath.ex_br_type := ex_reg_br_type ^ ex_reg_btb_hit
|
||||
io.dpath.ex_br_type := Mux(ex_reg_branch, ex_reg_br_type, BR_N) ^ io.dpath.ex_predicted_taken
|
||||
io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val
|
||||
io.dpath.ex_rocc_val := ex_reg_rocc_val
|
||||
io.dpath.mem_rocc_val := mem_reg_rocc_val
|
||||
|
||||
@ -57,6 +57,8 @@ object DecodeLogic
|
||||
}
|
||||
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
|
||||
apply(addr, Bool.DC, trues.map(_ -> Bool(true)) ++ falses.map(_ -> Bool(false)))
|
||||
def apply(addr: UInt, tru: UInt, fals: UInt): Bool =
|
||||
apply(addr, Seq(tru), Seq(fals))
|
||||
private val caches = collection.mutable.Map[Module,collection.mutable.Map[Term,Bool]]()
|
||||
}
|
||||
|
||||
|
||||
@ -118,8 +118,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
|
||||
}
|
||||
}
|
||||
|
||||
val ex_raddr1 = ex_reg_inst(19,15)
|
||||
val ex_raddr2 = ex_reg_inst(24,20)
|
||||
io.ctrl.ex_rs(0) := ex_reg_inst(19,15)
|
||||
io.ctrl.ex_rs(1) := ex_reg_inst(24,20)
|
||||
|
||||
val bypass = Vec.fill(NBYP)(Bits())
|
||||
bypass(BYP_0) := Bits(0)
|
||||
@ -171,7 +171,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
|
||||
}
|
||||
val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs(0), ex_reg_pc)
|
||||
val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(20,0).toSInt)
|
||||
val ex_br64 = ex_br_base + ex_br_offset
|
||||
val ex_br64 = (ex_br_base + ex_br_offset) & SInt(-2)
|
||||
val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs(0), ex_br64), vaSign(ex_reg_pc, ex_br64))
|
||||
val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0))
|
||||
|
||||
@ -289,11 +289,13 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
|
||||
io.rocc.cmd.bits.rs2 := wb_reg_rs2
|
||||
|
||||
// hook up I$
|
||||
io.imem.req.bits.currentpc := ex_reg_pc
|
||||
io.imem.req.bits.pc :=
|
||||
Mux(io.ctrl.sel_pc === PC_EX, ex_br_addr,
|
||||
Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
|
||||
wb_reg_pc)).toUInt // PC_WB
|
||||
io.imem.btb_update.bits.pc := ex_reg_pc
|
||||
io.imem.btb_update.bits.target := io.imem.req.bits.pc
|
||||
io.imem.btb_update.bits.returnAddr := io.dmem.req.bits.addr & SInt(-4)
|
||||
|
||||
// for hazard/bypass opportunity detection
|
||||
io.ctrl.ex_waddr := ex_reg_inst(11,7)
|
||||
|
||||
@ -26,15 +26,11 @@ case class ICacheConfig(sets: Int, assoc: Int,
|
||||
|
||||
class FrontendReq extends Bundle {
|
||||
val pc = UInt(width = VADDR_BITS+1)
|
||||
val mispredict = Bool()
|
||||
val taken = Bool()
|
||||
val currentpc = UInt(width = VADDR_BITS+1)
|
||||
}
|
||||
|
||||
class FrontendResp(implicit conf: ICacheConfig) extends Bundle {
|
||||
val pc = UInt(width = VADDR_BITS+1) // ID stage PC
|
||||
val data = Bits(width = conf.ibytes*8)
|
||||
val taken = Bool()
|
||||
val xcpt_ma = Bool()
|
||||
val xcpt_if = Bool()
|
||||
|
||||
@ -44,6 +40,8 @@ class FrontendResp(implicit conf: ICacheConfig) extends Bundle {
|
||||
class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
|
||||
val req = Valid(new FrontendReq)
|
||||
val resp = Decoupled(new FrontendResp).flip
|
||||
val btb_resp = Valid(new BTBResp()(conf.btb)).flip
|
||||
val btb_update = Valid(new BTBUpdate()(conf.btb))
|
||||
val ptw = new TLBPTWIO().flip
|
||||
val invalidate = Bool(OUTPUT)
|
||||
}
|
||||
@ -55,7 +53,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
|
||||
val mem = new UncachedTileLinkIO
|
||||
}
|
||||
|
||||
val btb = Module(new BTB(c.btb))
|
||||
val btb = Module(new BTB()(c.btb))
|
||||
val icache = Module(new ICache)
|
||||
val tlb = Module(new TLB(c.ntlb))
|
||||
|
||||
@ -64,16 +62,17 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
|
||||
val s1_same_block = Reg(Bool())
|
||||
val s2_valid = Reg(init=Bool(true))
|
||||
val s2_pc = Reg(init=UInt(START_ADDR))
|
||||
val s2_btb_hit = Reg(init=Bool(false))
|
||||
val s2_btb_resp_valid = Reg(init=Bool(false))
|
||||
val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
|
||||
val s2_xcpt_if = Reg(init=Bool(false))
|
||||
|
||||
val btbTarget = Cat(btb.io.target(VADDR_BITS-1), btb.io.target)
|
||||
val btbTarget = Cat(btb.io.resp.bits.target(VADDR_BITS-1), btb.io.resp.bits.target)
|
||||
val pcp4_0 = s1_pc + UInt(c.ibytes)
|
||||
val pcp4 = Cat(s1_pc(VADDR_BITS-1) & pcp4_0(VADDR_BITS-1), pcp4_0(VADDR_BITS-1,0))
|
||||
val icmiss = s2_valid && !icache.io.resp.valid
|
||||
val predicted_npc = btbTarget /* zero if btb miss */ | Mux(btb.io.hit, UInt(0), pcp4)
|
||||
val predicted_npc = btbTarget /* zero if btb miss */ | Mux(btb.io.resp.bits.taken, UInt(0), pcp4)
|
||||
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
|
||||
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.hit && ((pcp4 & (c.databits/8)) === (s1_pc & (c.databits/8)))
|
||||
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & (c.databits/8)) === (s1_pc & (c.databits/8)))
|
||||
|
||||
val stall = io.cpu.resp.valid && !io.cpu.resp.ready
|
||||
when (!stall) {
|
||||
@ -82,7 +81,8 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
|
||||
s2_valid := !icmiss
|
||||
when (!icmiss) {
|
||||
s2_pc := s1_pc
|
||||
s2_btb_hit := btb.io.hit
|
||||
s2_btb_resp_valid := btb.io.resp.valid
|
||||
when (btb.io.resp.valid) { s2_btb_resp_bits := btb.io.resp.bits }
|
||||
s2_xcpt_if := tlb.io.resp.xcpt_if
|
||||
}
|
||||
}
|
||||
@ -92,11 +92,8 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
|
||||
s2_valid := Bool(false)
|
||||
}
|
||||
|
||||
btb.io.current_pc := s1_pc
|
||||
btb.io.wen := io.cpu.req.bits.mispredict
|
||||
btb.io.taken := io.cpu.req.bits.taken
|
||||
btb.io.correct_pc := io.cpu.req.bits.currentpc
|
||||
btb.io.correct_target := io.cpu.req.bits.pc
|
||||
btb.io.req := s1_pc & SInt(-c.ibytes)
|
||||
btb.io.update := io.cpu.btb_update
|
||||
btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
|
||||
|
||||
tlb.io.ptw <> io.cpu.ptw
|
||||
@ -117,9 +114,11 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
|
||||
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
|
||||
io.cpu.resp.bits.pc := s2_pc & SInt(-c.ibytes) // discard PC LSBs
|
||||
io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8))
|
||||
io.cpu.resp.bits.taken := s2_btb_hit
|
||||
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UInt(0)
|
||||
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
|
||||
|
||||
io.cpu.btb_resp.valid := s2_btb_resp_valid
|
||||
io.cpu.btb_resp.bits := s2_btb_resp_bits
|
||||
}
|
||||
|
||||
class ICacheReq extends Bundle {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user