Add return address stack
This commit is contained in:
Andrew Waterman
@ -5,41 +5,80 @@ import Util._
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import Node._
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import uncore.constants.AddressConstants._
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case class BTBConfig(entries: Int) {
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case class BTBConfig(entries: Int, nras: Int = 0, inOrder: Boolean = true) {
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val matchBits = PGIDX_BITS
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val pages0 = 1 + log2Up(entries) // is this sensible? what about matchBits?
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val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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}
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class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = VADDR_BITS)
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val target = UInt(width = VADDR_BITS)
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val returnAddr = UInt(width = VADDR_BITS)
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val taken = Bool()
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val isCall = Bool()
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val isReturn = Bool()
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val incorrectTarget = Bool()
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override def clone = new BTBUpdate().asInstanceOf[this.type]
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}
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class BTBResp(implicit conf: BTBConfig) extends Bundle {
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val taken = Bool()
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val target = UInt(width = VADDR_BITS)
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val opaque = UInt(width = conf.opaqueBits)
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override def clone = new BTBResp().asInstanceOf[this.type]
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}
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class RAS(implicit conf: BTBConfig) {
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def push(addr: UInt): Unit = {
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when (count < conf.nras-1) { count := count + 1 }
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stack(pos+1) := addr
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pos := pos+1
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}
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def pop: UInt = {
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count := count - 1
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pos := pos - 1
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stack(pos)
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}
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def clear: Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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require(isPow2(conf.nras))
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private val count = Reg(init=UInt(0,log2Up(conf.nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(conf.nras)))
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private val stack = Vec.fill(conf.nras){Reg(UInt())}
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}
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// fully-associative branch target buffer
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class BTB(conf: BTBConfig) extends Module {
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class BTB(implicit conf: BTBConfig) extends Module {
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val io = new Bundle {
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val current_pc = UInt(INPUT, VADDR_BITS)
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val hit = Bool(OUTPUT)
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val target = UInt(OUTPUT, VADDR_BITS)
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val wen = Bool(INPUT)
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val taken = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val correct_pc = UInt(INPUT, VADDR_BITS)
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val correct_target = UInt(INPUT, VADDR_BITS)
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val req = UInt(INPUT, VADDR_BITS)
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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}
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val idxValid = Vec.fill(conf.entries){Reg(init=Bool(false))}
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val idxs = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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val pages = Vec.fill(conf.pages){Reg(UInt(width=VADDR_BITS-conf.matchBits))}
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val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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val useRAS = Vec.fill(conf.entries){Reg(Bool())}
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private def page(addr: UInt) = addr >> conf.matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid.toBits
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}
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private def tagMatch(addr: UInt): UInt = tagMatch(addr, pageMatch(addr))
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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val idx = addr(conf.matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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@ -47,13 +86,19 @@ class BTB(conf: BTBConfig) extends Module {
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idxValid.toBits & idxMatch & idxPageMatch
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}
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val hits = tagMatch(io.current_pc)
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val idxPageMatch = pageMatch(io.correct_pc)
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val tgtPageMatch = pageMatch(io.correct_target)
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val updates = tagMatch(io.correct_pc, idxPageMatch)
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val anyUpdates = updates.orR
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val update = Pipe(io.update)
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val update_target = io.req
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private var lfsr = LFSR16(io.wen)
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val pageHit = pageMatch(io.req)
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val hits = tagMatch(io.req, pageHit)
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val updatePageHit = pageMatch(update.bits.pc)
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val updateHits = tagMatch(update.bits.pc, updatePageHit)
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val taken = update.bits.incorrectTarget || update.bits.taken
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val predicted_taken = update.bits.prediction.valid && update.bits.prediction.bits.taken
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val correction = update.bits.incorrectTarget || update.bits.taken != predicted_taken
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private var lfsr = LFSR16(update.valid)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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@ -62,32 +107,35 @@ class BTB(conf: BTBConfig) extends Module {
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Mux(!valid.andR, PriorityEncoderOH(~valid), rand(valid.getWidth))
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val idxRepl = randOrInvalid(idxValid.toBits)
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val idxWen = updates.toBits | idxRepl & ~anyUpdates.toSInt
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val idxWen =
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if (conf.inOrder) Mux(update.bits.prediction.valid, UIntToOH(update.bits.prediction.bits.opaque), idxRepl)
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else updateHits | Mux(updateHits.orR, UInt(0), idxRepl)
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val useIdxPageMatch = idxPageMatch.orR
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val doIdxPageRepl = !useIdxPageMatch && io.taken
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = !useUpdatePageHit && update.valid
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val idxPageRepl = rand(conf.pages)
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val idxPageUpdate = Mux(useIdxPageMatch, idxPageMatch, idxPageRepl)
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val idxPageUpdate = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(io.correct_pc) === page(io.correct_target)
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val useTgtPageMatch = (tgtPageMatch & ~idxPageReplEn).orR
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val doTgtPageRepl = !useTgtPageMatch && io.taken && !samePage
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val samePage = page(update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = !usePageHit && !samePage && update.valid
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val tgtPageRepl = Mux(samePage, idxPageUpdate, idxPageUpdate(conf.pages-2,0) << 1 | idxPageUpdate(conf.pages-1))
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val tgtPageUpdate = Mux(useTgtPageMatch, tgtPageMatch, tgtPageRepl)
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val tgtPageUpdate = Mux(usePageHit, pageHit, tgtPageRepl)
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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when (io.wen) {
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when (update.valid) {
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for (i <- 0 until conf.entries) {
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when (idxWen(i)) {
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idxValid(i) := io.taken
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when (io.taken) {
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idxs(i) := io.correct_pc
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idxValid(i) := taken
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when (correction) {
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idxs(i) := update.bits.pc
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idxPages(i) := OHToUInt(idxPageUpdate)
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tgts(i) := io.correct_target
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tgts(i) := update_target
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tgtPages(i) := OHToUInt(tgtPageUpdate)
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useRAS(i) := update.bits.isReturn
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}
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}.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
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idxValid(i) := false
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@ -106,9 +154,9 @@ class BTB(conf: BTBConfig) extends Module {
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}
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}
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(io.correct_pc), page(io.correct_target)))
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Mux(idxWritesEven, page(update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(io.correct_target), page(io.correct_pc)))
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Mux(idxWritesEven, page(update_target), page(update.bits.pc)))
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}
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when (io.invalidate) {
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@ -116,6 +164,19 @@ class BTB(conf: BTBConfig) extends Module {
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pageValid.foreach(_ := false)
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}
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io.hit := hits.toBits.orR
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io.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.valid := hits.toBits.orR
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.opaque := OHToUInt(hits)
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if (conf.nras > 0) {
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val ras = new RAS
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when (!ras.isEmpty && Mux1H(hits, useRAS)) {
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io.resp.bits.target := ras.pop
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}
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when (io.update.valid && io.update.bits.isCall) {
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ras.push(io.update.bits.returnAddr)
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}
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when (io.invalidate) { ras.clear }
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}
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}
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