riscv/rocket-chip
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fixed console i/o

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This commit is contained in:
Rimas Avizienis 2011-11-30 22:51:59 -08:00
parent b2894671f6
commit da2fdf4f85
4 changed files with 12 additions and 7 deletions
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6
rocket/src/main/scala/cpu.scala
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@ -106,10 +106,8 @@ class rocketProc extends Component
dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag; dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
dpath.io.dmem.resp_data := arb.io.cpu.resp_data; dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
// FIXME: console disconnected io.console.bits := dpath.io.console.bits;
// io.console.bits := dpath.io.dpath.rs1(7,0); io.console.valid := dpath.io.console.valid;
io.console.bits := Bits(0,8);
io.console.valid := ctrl.io.console.valid;
ctrl.io.console.rdy := io.console.rdy; ctrl.io.console.rdy := io.console.rdy;
} }

4
rocket/src/main/scala/ctrl.scala
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@ -70,7 +70,7 @@ class ioCtrlDpath extends Bundle()
class ioCtrlAll extends Bundle() class ioCtrlAll extends Bundle()
{ {
val dpath = new ioCtrlDpath(); val dpath = new ioCtrlDpath();
val console = new ioConsole(List("rdy", "valid")); val console = new ioConsole(List("rdy"));
val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip(); val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss")).flip(); val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss")).flip();
val host = new ioHost(List("start")); val host = new ioHost(List("start"));
@ -299,8 +299,6 @@ class rocketCtrl extends Component
val id_ren1 = id_renx1; val id_ren1 = id_renx1;
val id_console_out_val = id_wen_pcr & (id_raddr2 === PCR_CONSOLE); val id_console_out_val = id_wen_pcr & (id_raddr2 === PCR_CONSOLE);
val console_out_fire = id_console_out_val & ~io.dpath.killd;
io.console.valid := console_out_fire.toBool;
val wb_reg_div_mul_val = Reg(){Bool()}; val wb_reg_div_mul_val = Reg(){Bool()};
val dcache_miss = Reg(io.dmem.resp_miss); val dcache_miss = Reg(io.dmem.resp_miss);

3
rocket/src/main/scala/dpath.scala
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@ -25,6 +25,7 @@ class ioDpathAll extends Bundle()
{ {
val host = new ioHost(); val host = new ioHost();
val ctrl = new ioCtrlDpath().flip(); val ctrl = new ioCtrlDpath().flip();
val console = new ioConsole(List("valid","bits"));
val debug = new ioDebug(); val debug = new ioDebug();
val dmem = new ioDpathDmem(); val dmem = new ioDpathDmem();
val imem = new ioDpathImem(); val imem = new ioDpathImem();
@ -442,6 +443,8 @@ class rocketDpath extends Component
pcr.io.cause := io.ctrl.cause; pcr.io.cause := io.ctrl.cause;
pcr.io.pc := mem_reg_pc; pcr.io.pc := mem_reg_pc;
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen; pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
io.console.bits := pcr.io.console_data;
io.console.valid := pcr.io.console_val;
} }
} }

6
rocket/src/main/scala/dpath_util.scala
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@ -57,6 +57,8 @@ class ioDpathPCR extends Bundle()
val ptbr_wen = Bool('output); val ptbr_wen = Bool('output);
val irq_timer = Bool('output); val irq_timer = Bool('output);
val irq_ipi = Bool('output); val irq_ipi = Bool('output);
val console_data = Bits(8, 'output);
val console_val = Bool('output);
} }
class rocketDpathPCR extends Component class rocketDpathPCR extends Component
@ -101,6 +103,10 @@ class rocketDpathPCR extends Component
io.debug.error_mode := reg_error_mode; io.debug.error_mode := reg_error_mode;
io.r.data := rdata; io.r.data := rdata;
val console_wen = !io.exception && io.w.en && (io.w.addr === PCR_CONSOLE);
io.console_data := Mux(console_wen, io.w.data(7,0), Bits(0,8));
io.console_val := console_wen;
when (io.host.from_wen) { when (io.host.from_wen) {
reg_tohost <== Bits(0,32); reg_tohost <== Bits(0,32);
reg_fromhost <== io.host.from; reg_fromhost <== io.host.from;