From da2fdf4f854f411b685eff1600264c1445b348eb Mon Sep 17 00:00:00 2001
From: Rimas Avizienis <rimas@eecs.berkeley.edu>
Date: Wed, 30 Nov 2011 22:51:59 -0800
Subject: [PATCH] fixed console i/o

---
 rocket/src/main/scala/cpu.scala        | 6 ++----
 rocket/src/main/scala/ctrl.scala       | 4 +---
 rocket/src/main/scala/dpath.scala      | 3 +++
 rocket/src/main/scala/dpath_util.scala | 6 ++++++
 4 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index e38f3813..602a0716 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -106,10 +106,8 @@ class rocketProc extends Component
   dpath.io.dmem.resp_tag  := arb.io.cpu.resp_tag;
   dpath.io.dmem.resp_data := arb.io.cpu.resp_data;  
 
-  // FIXME: console disconnected
-//   io.console.bits     := dpath.io.dpath.rs1(7,0);
-  io.console.bits     := Bits(0,8);
-  io.console.valid    := ctrl.io.console.valid;
+  io.console.bits     := dpath.io.console.bits;
+  io.console.valid    := dpath.io.console.valid;
   ctrl.io.console.rdy := io.console.rdy;
 }
 
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 680a68f7..8cf3d8f3 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -70,7 +70,7 @@ class ioCtrlDpath extends Bundle()
 class ioCtrlAll extends Bundle()
 {
   val dpath   = new ioCtrlDpath();
-  val console = new ioConsole(List("rdy", "valid"));
+  val console = new ioConsole(List("rdy"));
   val imem    = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
   val dmem    = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss")).flip();
   val host    = new ioHost(List("start"));
@@ -299,8 +299,6 @@ class rocketCtrl extends Component
   val id_ren1 = id_renx1;
 
   val id_console_out_val  = id_wen_pcr & (id_raddr2 === PCR_CONSOLE);
-  val console_out_fire    = id_console_out_val & ~io.dpath.killd;
-  io.console.valid        := console_out_fire.toBool;
 
   val wb_reg_div_mul_val = Reg(){Bool()};
   val dcache_miss =   Reg(io.dmem.resp_miss);
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 56c044d8..5041395f 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -25,6 +25,7 @@ class ioDpathAll extends Bundle()
 {
   val host  = new ioHost();
   val ctrl  = new ioCtrlDpath().flip();
+  val console = new ioConsole(List("valid","bits"));
   val debug = new ioDebug();
   val dmem  = new ioDpathDmem();
   val imem  = new ioDpathImem();
@@ -442,6 +443,8 @@ class rocketDpath extends Component
   pcr.io.cause 			  := io.ctrl.cause;
   pcr.io.pc					  := mem_reg_pc;
   pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
+  io.console.bits := pcr.io.console_data;
+  io.console.valid := pcr.io.console_val;
 }
 
 }
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 751bf796..9f6e9cc7 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -57,6 +57,8 @@ class ioDpathPCR extends Bundle()
   val ptbr_wen  = Bool('output);
   val irq_timer = Bool('output);
   val irq_ipi   = Bool('output);
+  val console_data = Bits(8, 'output);
+  val console_val  = Bool('output);
 }
 
 class rocketDpathPCR extends Component
@@ -101,6 +103,10 @@ class rocketDpathPCR extends Component
   io.debug.error_mode  	:= reg_error_mode;
   io.r.data := rdata;
 
+  val console_wen = !io.exception && io.w.en && (io.w.addr === PCR_CONSOLE);
+  io.console_data := Mux(console_wen, io.w.data(7,0), Bits(0,8));
+  io.console_val := console_wen;
+
   when (io.host.from_wen) {
     reg_tohost   <== Bits(0,32);
     reg_fromhost <== io.host.from;