nodes: grab a name on construction
This commit is contained in:
Wesley W. Terpstra
parent
3656e975a1
commit
d89ee9d9d4
@ -25,23 +25,24 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A
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}
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// Nodes implemented inside modules
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case class AHBIdentityNode() extends IdentityNode(AHBImp)
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case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters]) extends SourceNode(AHBImp)(portParams)
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case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters]) extends SinkNode(AHBImp)(portParams)
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case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp)
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case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImp)(portParams)
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case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImp)(portParams)
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case class AHBNexusNode(
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masterFn: Seq[AHBMasterPortParameters] => AHBMasterPortParameters,
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slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters,
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numMasterPorts: Range.Inclusive = 1 to 999,
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numSlavePorts: Range.Inclusive = 1 to 999)
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numSlavePorts: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends NexusNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
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// Nodes passed from an inner module
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case class AHBOutputNode() extends OutputNode(AHBImp)
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case class AHBInputNode() extends InputNode(AHBImp)
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case class AHBOutputNode()(implicit valName: ValName) extends OutputNode(AHBImp)
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case class AHBInputNode()(implicit valName: ValName) extends InputNode(AHBImp)
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// Nodes used for external ports
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case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters]) extends BlindOutputNode(AHBImp)(portParams)
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case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters]) extends BlindInputNode(AHBImp)(portParams)
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case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AHBImp)(portParams)
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case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AHBImp)(portParams)
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case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters]) extends InternalOutputNode(AHBImp)(portParams)
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case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters]) extends InternalInputNode(AHBImp)(portParams)
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case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AHBImp)(portParams)
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case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AHBImp)(portParams)
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@ -10,8 +10,8 @@ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
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import freechips.rocketchip.util.{HeterogeneousBag, MaskGen}
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import scala.math.{min,max}
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class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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extends AHBSlaveNode(Seq(AHBSlavePortParameters(
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case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
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extends SinkNode(AHBImp)(Seq(AHBSlavePortParameters(
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Seq(AHBSlaveParameters(
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address = Seq(address),
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executable = executable,
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@ -67,12 +67,6 @@ class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
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}
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}
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object AHBRegisterNode
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{
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
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new AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a AHB
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// register mapped device from a totally abstract register mapped device.
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@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.MaskGen
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case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)(
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case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImp, TLImp)(
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dFn = { case AHBMasterPortParameters(masters) =>
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TLClientPortParameters(clients = masters.map { m =>
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TLClientParameters(name = m.name, nodePath = m.nodePath)
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@ -26,23 +26,24 @@ object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, A
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}
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// Nodes implemented inside modules
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case class APBIdentityNode() extends IdentityNode(APBImp)
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case class APBMasterNode(portParams: Seq[APBMasterPortParameters]) extends SourceNode(APBImp)(portParams)
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case class APBSlaveNode(portParams: Seq[APBSlavePortParameters]) extends SinkNode(APBImp)(portParams)
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case class APBIdentityNode()(implicit valName: ValName) extends IdentityNode(APBImp)
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case class APBMasterNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends SourceNode(APBImp)(portParams)
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case class APBSlaveNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends SinkNode(APBImp)(portParams)
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case class APBNexusNode(
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masterFn: Seq[APBMasterPortParameters] => APBMasterPortParameters,
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slaveFn: Seq[APBSlavePortParameters] => APBSlavePortParameters,
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numMasterPorts: Range.Inclusive = 1 to 1,
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numSlavePorts: Range.Inclusive = 1 to 1)
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numSlavePorts: Range.Inclusive = 1 to 1)(
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implicit valName: ValName)
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extends NexusNode(APBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
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// Nodes passed from an inner module
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case class APBOutputNode() extends OutputNode(APBImp)
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case class APBInputNode() extends InputNode(APBImp)
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case class APBOutputNode()(implicit valName: ValName) extends OutputNode(APBImp)
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case class APBInputNode()(implicit valName: ValName) extends InputNode(APBImp)
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// Nodes used for external ports
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case class APBBlindOutputNode(portParams: Seq[APBSlavePortParameters]) extends BlindOutputNode(APBImp)(portParams)
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case class APBBlindInputNode(portParams: Seq[APBMasterPortParameters]) extends BlindInputNode(APBImp)(portParams)
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case class APBBlindOutputNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(APBImp)(portParams)
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case class APBBlindInputNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(APBImp)(portParams)
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case class APBInternalOutputNode(portParams: Seq[APBSlavePortParameters]) extends InternalOutputNode(APBImp)(portParams)
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case class APBInternalInputNode(portParams: Seq[APBMasterPortParameters]) extends InternalInputNode(APBImp)(portParams)
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case class APBInternalOutputNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(APBImp)(portParams)
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case class APBInternalInputNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(APBImp)(portParams)
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@ -10,8 +10,8 @@ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
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import freechips.rocketchip.util.HeterogeneousBag
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import scala.math.{min,max}
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class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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extends APBSlaveNode(Seq(APBSlavePortParameters(
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case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
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extends SinkNode(APBImp)(Seq(APBSlavePortParameters(
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Seq(APBSlaveParameters(
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address = Seq(address),
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executable = executable,
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@ -51,12 +51,6 @@ class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
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}
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}
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object APBRegisterNode
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{
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
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new APBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a APB
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// register mapped device from a totally abstract register mapped device.
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@ -26,22 +26,23 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
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}
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// Nodes implemented inside modules
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case class AXI4IdentityNode() extends IdentityNode(AXI4Imp)
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case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters]) extends SourceNode(AXI4Imp)(portParams)
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case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters]) extends SinkNode(AXI4Imp)(portParams)
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case class AXI4IdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4Imp)
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case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams)
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case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams)
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case class AXI4AdapterNode(
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masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters,
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slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters,
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numPorts: Range.Inclusive = 0 to 999)
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numPorts: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts)
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// Nodes passed from an inner module
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case class AXI4OutputNode() extends OutputNode(AXI4Imp)
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case class AXI4InputNode() extends InputNode(AXI4Imp)
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case class AXI4OutputNode()(implicit valName: ValName) extends OutputNode(AXI4Imp)
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case class AXI4InputNode()(implicit valName: ValName) extends InputNode(AXI4Imp)
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// Nodes used for external ports
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case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends BlindOutputNode(AXI4Imp)(portParams)
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case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters]) extends BlindInputNode(AXI4Imp)(portParams)
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case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AXI4Imp)(portParams)
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case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AXI4Imp)(portParams)
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case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends InternalOutputNode(AXI4Imp)(portParams)
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case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters]) extends InternalInputNode(AXI4Imp)(portParams)
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case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AXI4Imp)(portParams)
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case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AXI4Imp)(portParams)
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@ -10,8 +10,8 @@ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
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import freechips.rocketchip.util.{HeterogeneousBag, MaskGen}
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import scala.math.{min,max}
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class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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extends AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
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extends SinkNode(AXI4Imp)(Seq(AXI4SlavePortParameters(
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Seq(AXI4SlaveParameters(
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address = Seq(address),
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executable = executable,
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@ -77,12 +77,6 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
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}
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}
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object AXI4RegisterNode
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{
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
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new AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a AXI4
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// register mapped device from a totally abstract register mapped device.
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@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
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case class AXI4ToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)(
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dFn = { case AXI4MasterPortParameters(masters, userBits) =>
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masters.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") }
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val maxFlight = masters.map(_.maxFlight.get).max
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@ -67,7 +67,7 @@ trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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abstract class NodeImp[D, U, EO, EI, B <: Data]
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extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
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abstract class BaseNode
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abstract class BaseNode(implicit val valName: ValName)
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{
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require (!LazyModule.stack.isEmpty, "You cannot create a node outside a LazyModule!")
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@ -178,7 +178,8 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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protected[diplomacy] val numPO: Range.Inclusive,
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protected[diplomacy] val numPI: Range.Inclusive)
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protected[diplomacy] val numPI: Range.Inclusive)(
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implicit valName: ValName)
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extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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{
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
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@ -308,7 +309,8 @@ abstract class MixedCustomNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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numPI: Range.Inclusive)(
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implicit valName: ValName)
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extends MixedNode(inner, outer)(numPO, numPI)
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{
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def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int)
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@ -318,7 +320,8 @@ abstract class MixedCustomNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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abstract class CustomNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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numPI: Range.Inclusive)(
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implicit valName: ValName)
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extends MixedCustomNode(imp, imp)(numPO, numPI)
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class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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@ -326,7 +329,8 @@ class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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dFn: DI => DO,
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uFn: UO => UI,
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num: Range.Inclusive = 0 to 999)
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num: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends MixedNode(inner, outer)(num, num)
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{
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val externalIn: Boolean = true
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@ -358,7 +362,8 @@ class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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dFn: Seq[DI] => DO,
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uFn: Seq[UO] => UI,
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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numPI: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends MixedNode(inner, outer)(numPO, numPI)
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{
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// require (numPO.end >= 1, s"${name} does not accept outputs${lazyModule.line}")
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@ -379,14 +384,16 @@ class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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class AdapterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: D => D,
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uFn: U => U,
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num: Range.Inclusive = 0 to 999)
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num: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends MixedAdapterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, num)
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class NexusNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: Seq[D] => D,
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uFn: Seq[U] => U,
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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numPI: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends MixedNexusNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI)
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case class SplitterArg[T](newSize: Int, ports: Seq[T])
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@ -396,7 +403,8 @@ class MixedSplitterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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dFn: SplitterArg[DI] => Seq[DO],
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uFn: SplitterArg[UO] => Seq[UI],
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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numPI: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends MixedNode(inner, outer)(numPO, numPI)
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{
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override val externalIn: Boolean = true
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@ -425,20 +433,21 @@ class SplitterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: SplitterArg[D] => Seq[D],
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uFn: SplitterArg[U] => Seq[U],
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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numPI: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends MixedSplitterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI)
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class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])
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class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName)
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extends AdapterNode(imp)({s => s}, {s => s})
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class OutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends IdentityNode(imp)
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class OutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends IdentityNode(imp)
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{
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override val externalIn: Boolean = false
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override val externalOut: Boolean = true
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override lazy val bundleIn = bundleOut
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}
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class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends IdentityNode(imp)
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class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends IdentityNode(imp)
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{
|
||||
override val externalIn: Boolean = true
|
||||
override val externalOut: Boolean = false
|
||||
@ -446,7 +455,7 @@ class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends
|
||||
override lazy val bundleOut = bundleIn
|
||||
}
|
||||
|
||||
class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])
|
||||
class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName)
|
||||
extends MixedNode(imp, imp)(po.size to po.size, 0 to 0)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
@ -465,7 +474,7 @@ class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq
|
||||
override lazy val bundleIn = { require(false, s"${name} has no bundleIn; try bundleOut?"); bundleOut }
|
||||
}
|
||||
|
||||
class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])
|
||||
class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName)
|
||||
extends MixedNode(imp, imp)(0 to 0, pi.size to pi.size)
|
||||
{
|
||||
override val externalIn: Boolean = true
|
||||
@ -484,7 +493,7 @@ class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U
|
||||
override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn }
|
||||
}
|
||||
|
||||
class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])
|
||||
class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName)
|
||||
extends SinkNode(imp)(pi)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
@ -492,7 +501,7 @@ class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi
|
||||
override lazy val bundleOut = bundleIn
|
||||
}
|
||||
|
||||
class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])
|
||||
class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName)
|
||||
extends SourceNode(imp)(po)
|
||||
{
|
||||
override val externalOut: Boolean = false
|
||||
@ -500,7 +509,7 @@ class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po:
|
||||
override lazy val bundleIn = bundleOut
|
||||
}
|
||||
|
||||
class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])
|
||||
class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName)
|
||||
extends SinkNode(imp)(pi)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
@ -509,7 +518,7 @@ class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])
|
||||
override lazy val bundleOut = bundleIn
|
||||
}
|
||||
|
||||
class InternalInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])
|
||||
class InternalInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName)
|
||||
extends SourceNode(imp)(po)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
|
||||
@ -244,7 +244,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
|
||||
val masterNode = TLOutputNode()
|
||||
masterNode :=* optionalMasterBuffer(rocket.masterNode)
|
||||
|
||||
val slaveNode = new TLInputNode() { override def reverse = true }
|
||||
val slaveNode = new TLInputNode()(ValName("slave")) { override def reverse = true }
|
||||
DisableMonitors { implicit p => rocket.slaveNode :*= optionalSlaveBuffer(slaveNode) }
|
||||
|
||||
// Fully async interrupts need synchronizers.
|
||||
@ -265,7 +265,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
|
||||
source.node :=* rocket.masterNode
|
||||
masterNode :=* source.node
|
||||
|
||||
val slaveNode = new TLAsyncInputNode() { override def reverse = true }
|
||||
val slaveNode = new TLAsyncInputNode()(ValName("slave")) { override def reverse = true }
|
||||
val sink = LazyModule(new TLAsyncCrossingSink)
|
||||
|
||||
DisableMonitors { implicit p =>
|
||||
@ -294,7 +294,7 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
|
||||
source.node :=* optionalMasterBuffer(rocket.masterNode)
|
||||
masterNode :=* source.node
|
||||
|
||||
val slaveNode = new TLRationalInputNode() { override def reverse = true }
|
||||
val slaveNode = new TLRationalInputNode()(ValName("slave")) { override def reverse = true }
|
||||
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
|
||||
|
||||
DisableMonitors { implicit p =>
|
||||
|
||||
@ -13,7 +13,7 @@ class TLBufferNode (
|
||||
b: BufferParams,
|
||||
c: BufferParams,
|
||||
d: BufferParams,
|
||||
e: BufferParams)(implicit p: Parameters) extends TLAdapterNode(
|
||||
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
|
||||
clientFn = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
|
||||
managerFn = { p => p.copy(minLatency = p.minLatency + a.latency + d.latency) }
|
||||
) {
|
||||
|
||||
@ -88,25 +88,26 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
|
||||
pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
|
||||
}
|
||||
|
||||
case class IntIdentityNode() extends IdentityNode(IntImp)
|
||||
case class IntSourceNode(portParams: Seq[IntSourcePortParameters]) extends SourceNode(IntImp)(portParams)
|
||||
case class IntSinkNode(portParams: Seq[IntSinkPortParameters]) extends SinkNode(IntImp)(portParams)
|
||||
case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)
|
||||
case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams)
|
||||
case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams)
|
||||
|
||||
case class IntNexusNode(
|
||||
sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
|
||||
sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters,
|
||||
numSourcePorts: Range.Inclusive = 0 to 128,
|
||||
numSinkPorts: Range.Inclusive = 0 to 128)
|
||||
numSinkPorts: Range.Inclusive = 0 to 128)(
|
||||
implicit valName: ValName)
|
||||
extends NexusNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
|
||||
|
||||
case class IntOutputNode() extends OutputNode(IntImp)
|
||||
case class IntInputNode() extends InputNode(IntImp)
|
||||
case class IntOutputNode()(implicit valName: ValName) extends OutputNode(IntImp)
|
||||
case class IntInputNode()(implicit valName: ValName) extends InputNode(IntImp)
|
||||
|
||||
case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters]) extends BlindOutputNode(IntImp)(portParams)
|
||||
case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters]) extends BlindInputNode(IntImp)(portParams)
|
||||
case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends BlindOutputNode(IntImp)(portParams)
|
||||
case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends BlindInputNode(IntImp)(portParams)
|
||||
|
||||
case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters]) extends InternalOutputNode(IntImp)(portParams)
|
||||
case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters]) extends InternalInputNode(IntImp)(portParams)
|
||||
case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends InternalOutputNode(IntImp)(portParams)
|
||||
case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends InternalInputNode(IntImp)(portParams)
|
||||
|
||||
class IntXbar()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
|
||||
@ -7,7 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None) extends TLCustomNode(0 to 999, 0 to 999)
|
||||
case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None)(implicit valName: ValName) extends TLCustomNode(0 to 999, 0 to 999)
|
||||
{
|
||||
val externalIn = true
|
||||
val externalOut = true
|
||||
|
||||
@ -64,57 +64,61 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
|
||||
}
|
||||
|
||||
// Nodes implemented inside modules
|
||||
case class TLIdentityNode() extends IdentityNode(TLImp)
|
||||
case class TLClientNode(portParams: Seq[TLClientPortParameters]) extends SourceNode(TLImp)(portParams)
|
||||
case class TLManagerNode(portParams: Seq[TLManagerPortParameters]) extends SinkNode(TLImp)(portParams)
|
||||
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)
|
||||
case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams)
|
||||
case class TLManagerNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams)
|
||||
|
||||
object TLClientNode
|
||||
{
|
||||
def apply(params: TLClientParameters) =
|
||||
def apply(params: TLClientParameters)(implicit valName: ValName) =
|
||||
new TLClientNode(Seq(TLClientPortParameters(Seq(params))))
|
||||
}
|
||||
|
||||
object TLManagerNode
|
||||
{
|
||||
def apply(beatBytes: Int, params: TLManagerParameters) =
|
||||
def apply(beatBytes: Int, params: TLManagerParameters)(implicit valName: ValName) =
|
||||
new TLManagerNode(Seq(TLManagerPortParameters(Seq(params), beatBytes, minLatency = 0)))
|
||||
}
|
||||
|
||||
case class TLAdapterNode(
|
||||
clientFn: TLClientPortParameters => TLClientPortParameters,
|
||||
managerFn: TLManagerPortParameters => TLManagerPortParameters,
|
||||
num: Range.Inclusive = 0 to 999)
|
||||
num: Range.Inclusive = 0 to 999)(
|
||||
implicit valName: ValName)
|
||||
extends AdapterNode(TLImp)(clientFn, managerFn, num)
|
||||
|
||||
case class TLNexusNode(
|
||||
clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
|
||||
managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
|
||||
numClientPorts: Range.Inclusive = 1 to 999,
|
||||
numManagerPorts: Range.Inclusive = 1 to 999)
|
||||
numManagerPorts: Range.Inclusive = 1 to 999)(
|
||||
implicit valName: ValName)
|
||||
extends NexusNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
|
||||
|
||||
case class TLSplitterNode(
|
||||
clientFn: SplitterArg[TLClientPortParameters] => Seq[TLClientPortParameters],
|
||||
managerFn: SplitterArg[TLManagerPortParameters] => Seq[TLManagerPortParameters],
|
||||
numClientPorts: Range.Inclusive = 0 to 999,
|
||||
numManagerPorts: Range.Inclusive = 0 to 999)
|
||||
numManagerPorts: Range.Inclusive = 0 to 999)(
|
||||
implicit valName: ValName)
|
||||
extends SplitterNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
|
||||
|
||||
abstract class TLCustomNode(
|
||||
numClientPorts: Range.Inclusive,
|
||||
numManagerPorts: Range.Inclusive)
|
||||
numManagerPorts: Range.Inclusive)(
|
||||
implicit valName: ValName)
|
||||
extends CustomNode(TLImp)(numClientPorts, numManagerPorts)
|
||||
|
||||
// Nodes passed from an inner module
|
||||
case class TLOutputNode() extends OutputNode(TLImp)
|
||||
case class TLInputNode() extends InputNode(TLImp)
|
||||
case class TLOutputNode()(implicit valName: ValName) extends OutputNode(TLImp)
|
||||
case class TLInputNode()(implicit valName: ValName) extends InputNode(TLImp)
|
||||
|
||||
// Nodes used for external ports
|
||||
case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters]) extends BlindOutputNode(TLImp)(portParams)
|
||||
case class TLBlindInputNode(portParams: Seq[TLClientPortParameters]) extends BlindInputNode(TLImp)(portParams)
|
||||
case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends BlindOutputNode(TLImp)(portParams)
|
||||
case class TLBlindInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends BlindInputNode(TLImp)(portParams)
|
||||
|
||||
case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters]) extends InternalOutputNode(TLImp)(portParams)
|
||||
case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends InternalInputNode(TLImp)(portParams)
|
||||
case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends InternalOutputNode(TLImp)(portParams)
|
||||
case class TLInternalInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends InternalInputNode(TLImp)(portParams)
|
||||
|
||||
/** Synthesizeable unit tests */
|
||||
import freechips.rocketchip.unittest._
|
||||
@ -156,16 +160,16 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
|
||||
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
|
||||
}
|
||||
|
||||
case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
|
||||
case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
|
||||
case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
|
||||
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)
|
||||
case class TLAsyncOutputNode()(implicit valName: ValName) extends OutputNode(TLAsyncImp)
|
||||
case class TLAsyncInputNode()(implicit valName: ValName) extends InputNode(TLAsyncImp)
|
||||
|
||||
case class TLAsyncSourceNode(sync: Int)
|
||||
case class TLAsyncSourceNode(sync: Int)(implicit valName: ValName)
|
||||
extends MixedAdapterNode(TLImp, TLAsyncImp)(
|
||||
dFn = { p => TLAsyncClientPortParameters(p) },
|
||||
uFn = { p => p.base.copy(minLatency = sync+1) }) // discard cycles in other clock domain
|
||||
|
||||
case class TLAsyncSinkNode(depth: Int, sync: Int)
|
||||
case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName)
|
||||
extends MixedAdapterNode(TLAsyncImp, TLImp)(
|
||||
dFn = { p => p.base.copy(minLatency = sync+1) },
|
||||
uFn = { p => TLAsyncManagerPortParameters(depth, p) })
|
||||
@ -186,16 +190,16 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM
|
||||
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
|
||||
}
|
||||
|
||||
case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp)
|
||||
case class TLRationalOutputNode() extends OutputNode(TLRationalImp)
|
||||
case class TLRationalInputNode() extends InputNode(TLRationalImp)
|
||||
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)
|
||||
case class TLRationalOutputNode()(implicit valName: ValName) extends OutputNode(TLRationalImp)
|
||||
case class TLRationalInputNode()(implicit valName: ValName) extends InputNode(TLRationalImp)
|
||||
|
||||
case class TLRationalSourceNode()
|
||||
case class TLRationalSourceNode()(implicit valName: ValName)
|
||||
extends MixedAdapterNode(TLImp, TLRationalImp)(
|
||||
dFn = { p => TLRationalClientPortParameters(p) },
|
||||
uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain
|
||||
|
||||
case class TLRationalSinkNode(direction: RationalDirection)
|
||||
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
|
||||
extends MixedAdapterNode(TLRationalImp, TLImp)(
|
||||
dFn = { p => p.base.copy(minLatency = 1) },
|
||||
uFn = { p => TLRationalManagerPortParameters(direction, p) })
|
||||
|
||||
@ -9,15 +9,16 @@ import freechips.rocketchip.regmapper._
|
||||
import freechips.rocketchip.util.HeterogeneousBag
|
||||
import scala.math.{min,max}
|
||||
|
||||
class TLRegisterNode(
|
||||
case class TLRegisterNode(
|
||||
address: Seq[AddressSet],
|
||||
device: Device,
|
||||
deviceKey: String = "reg/control",
|
||||
concurrency: Int = 0,
|
||||
beatBytes: Int = 4,
|
||||
undefZero: Boolean = true,
|
||||
executable: Boolean = false)
|
||||
extends TLManagerNode(Seq(TLManagerPortParameters(
|
||||
executable: Boolean = false)(
|
||||
implicit valName: ValName)
|
||||
extends SinkNode(TLImp)(Seq(TLManagerPortParameters(
|
||||
Seq(TLManagerParameters(
|
||||
address = address,
|
||||
resources = Seq(Resource(device, deviceKey)),
|
||||
@ -81,20 +82,6 @@ class TLRegisterNode(
|
||||
}
|
||||
}
|
||||
|
||||
object TLRegisterNode
|
||||
{
|
||||
def apply(
|
||||
address: Seq[AddressSet],
|
||||
device: Device,
|
||||
deviceKey: String = "reg/control",
|
||||
concurrency: Int = 0,
|
||||
beatBytes: Int = 4,
|
||||
undefZero: Boolean = true,
|
||||
executable: Boolean = false) =
|
||||
new TLRegisterNode(address, device, deviceKey, concurrency, beatBytes, undefZero, executable)
|
||||
}
|
||||
|
||||
// These convenience methods below combine to make it possible to create a TL2
|
||||
// register mapped device from a totally abstract register mapped device.
|
||||
// See GPIO.scala in this directory for an example
|
||||
|
||||
|
||||
@ -11,7 +11,7 @@ import freechips.rocketchip.util._
|
||||
import scala.math.{min, max}
|
||||
import AHBParameters._
|
||||
|
||||
case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
|
||||
case class TLToAHBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImp)(
|
||||
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
|
||||
val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
|
||||
AHBMasterPortParameters(masters)
|
||||
|
||||
@ -10,7 +10,7 @@ import freechips.rocketchip.amba.apb._
|
||||
import scala.math.{min, max}
|
||||
import APBParameters._
|
||||
|
||||
case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
|
||||
case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)(
|
||||
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
|
||||
val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
|
||||
APBMasterPortParameters(masters)
|
||||
|
||||
@ -10,7 +10,7 @@ import freechips.rocketchip.util._
|
||||
import freechips.rocketchip.amba.axi4._
|
||||
import scala.math.{min, max}
|
||||
|
||||
case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0) extends MixedAdapterNode(TLImp, AXI4Imp)(
|
||||
case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
|
||||
dFn = { p =>
|
||||
p.clients.foreach { c =>
|
||||
require (c.sourceId.start % (1 << stripBits) == 0 &&
|
||||
|
||||
Loading…
Reference in New Issue
Block a user