From d89ee9d9d4c2dae9bbbd3253bf73e9b1a81b74bc Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 11 Sep 2017 23:33:44 -0700 Subject: [PATCH] nodes: grab a name on construction --- src/main/scala/amba/ahb/Nodes.scala | 21 ++++---- src/main/scala/amba/ahb/RegisterRouter.scala | 10 +--- src/main/scala/amba/ahb/ToTL.scala | 2 +- src/main/scala/amba/apb/Nodes.scala | 21 ++++---- src/main/scala/amba/apb/RegisterRouter.scala | 10 +--- src/main/scala/amba/axi4/Nodes.scala | 21 ++++---- src/main/scala/amba/axi4/RegisterRouter.scala | 10 +--- src/main/scala/amba/axi4/ToTL.scala | 2 +- src/main/scala/diplomacy/Nodes.scala | 47 +++++++++------- src/main/scala/tile/RocketTile.scala | 6 +-- src/main/scala/tilelink/Buffer.scala | 2 +- src/main/scala/tilelink/IntNodes.scala | 21 ++++---- src/main/scala/tilelink/NodeNumberer.scala | 2 +- src/main/scala/tilelink/Nodes.scala | 54 ++++++++++--------- src/main/scala/tilelink/RegisterRouter.scala | 21 ++------ src/main/scala/tilelink/ToAHB.scala | 2 +- src/main/scala/tilelink/ToAPB.scala | 2 +- src/main/scala/tilelink/ToAXI4.scala | 2 +- 18 files changed, 121 insertions(+), 135 deletions(-) diff --git a/src/main/scala/amba/ahb/Nodes.scala b/src/main/scala/amba/ahb/Nodes.scala index 86671b45..7cbc8fc6 100644 --- a/src/main/scala/amba/ahb/Nodes.scala +++ b/src/main/scala/amba/ahb/Nodes.scala @@ -25,23 +25,24 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A } // Nodes implemented inside modules -case class AHBIdentityNode() extends IdentityNode(AHBImp) -case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters]) extends SourceNode(AHBImp)(portParams) -case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters]) extends SinkNode(AHBImp)(portParams) +case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp) +case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImp)(portParams) +case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImp)(portParams) case class AHBNexusNode( masterFn: Seq[AHBMasterPortParameters] => AHBMasterPortParameters, slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters, numMasterPorts: Range.Inclusive = 1 to 999, - numSlavePorts: Range.Inclusive = 1 to 999) + numSlavePorts: Range.Inclusive = 1 to 999)( + implicit valName: ValName) extends NexusNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts) // Nodes passed from an inner module -case class AHBOutputNode() extends OutputNode(AHBImp) -case class AHBInputNode() extends InputNode(AHBImp) +case class AHBOutputNode()(implicit valName: ValName) extends OutputNode(AHBImp) +case class AHBInputNode()(implicit valName: ValName) extends InputNode(AHBImp) // Nodes used for external ports -case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters]) extends BlindOutputNode(AHBImp)(portParams) -case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters]) extends BlindInputNode(AHBImp)(portParams) +case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AHBImp)(portParams) +case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AHBImp)(portParams) -case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters]) extends InternalOutputNode(AHBImp)(portParams) -case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters]) extends InternalInputNode(AHBImp)(portParams) +case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AHBImp)(portParams) +case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AHBImp)(portParams) diff --git a/src/main/scala/amba/ahb/RegisterRouter.scala b/src/main/scala/amba/ahb/RegisterRouter.scala index 0b9b19ea..720e2162 100644 --- a/src/main/scala/amba/ahb/RegisterRouter.scala +++ b/src/main/scala/amba/ahb/RegisterRouter.scala @@ -10,8 +10,8 @@ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.{HeterogeneousBag, MaskGen} import scala.math.{min,max} -class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) - extends AHBSlaveNode(Seq(AHBSlavePortParameters( +case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName) + extends SinkNode(AHBImp)(Seq(AHBSlavePortParameters( Seq(AHBSlaveParameters( address = Seq(address), executable = executable, @@ -67,12 +67,6 @@ class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int } } -object AHBRegisterNode -{ - def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) = - new AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable) -} - // These convenience methods below combine to make it possible to create a AHB // register mapped device from a totally abstract register mapped device. diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala index d63f8f38..c18eab94 100644 --- a/src/main/scala/amba/ahb/ToTL.scala +++ b/src/main/scala/amba/ahb/ToTL.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.MaskGen -case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)( +case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImp, TLImp)( dFn = { case AHBMasterPortParameters(masters) => TLClientPortParameters(clients = masters.map { m => TLClientParameters(name = m.name, nodePath = m.nodePath) diff --git a/src/main/scala/amba/apb/Nodes.scala b/src/main/scala/amba/apb/Nodes.scala index a3618129..9364077c 100644 --- a/src/main/scala/amba/apb/Nodes.scala +++ b/src/main/scala/amba/apb/Nodes.scala @@ -26,23 +26,24 @@ object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, A } // Nodes implemented inside modules -case class APBIdentityNode() extends IdentityNode(APBImp) -case class APBMasterNode(portParams: Seq[APBMasterPortParameters]) extends SourceNode(APBImp)(portParams) -case class APBSlaveNode(portParams: Seq[APBSlavePortParameters]) extends SinkNode(APBImp)(portParams) +case class APBIdentityNode()(implicit valName: ValName) extends IdentityNode(APBImp) +case class APBMasterNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends SourceNode(APBImp)(portParams) +case class APBSlaveNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends SinkNode(APBImp)(portParams) case class APBNexusNode( masterFn: Seq[APBMasterPortParameters] => APBMasterPortParameters, slaveFn: Seq[APBSlavePortParameters] => APBSlavePortParameters, numMasterPorts: Range.Inclusive = 1 to 1, - numSlavePorts: Range.Inclusive = 1 to 1) + numSlavePorts: Range.Inclusive = 1 to 1)( + implicit valName: ValName) extends NexusNode(APBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts) // Nodes passed from an inner module -case class APBOutputNode() extends OutputNode(APBImp) -case class APBInputNode() extends InputNode(APBImp) +case class APBOutputNode()(implicit valName: ValName) extends OutputNode(APBImp) +case class APBInputNode()(implicit valName: ValName) extends InputNode(APBImp) // Nodes used for external ports -case class APBBlindOutputNode(portParams: Seq[APBSlavePortParameters]) extends BlindOutputNode(APBImp)(portParams) -case class APBBlindInputNode(portParams: Seq[APBMasterPortParameters]) extends BlindInputNode(APBImp)(portParams) +case class APBBlindOutputNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(APBImp)(portParams) +case class APBBlindInputNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(APBImp)(portParams) -case class APBInternalOutputNode(portParams: Seq[APBSlavePortParameters]) extends InternalOutputNode(APBImp)(portParams) -case class APBInternalInputNode(portParams: Seq[APBMasterPortParameters]) extends InternalInputNode(APBImp)(portParams) +case class APBInternalOutputNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(APBImp)(portParams) +case class APBInternalInputNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(APBImp)(portParams) diff --git a/src/main/scala/amba/apb/RegisterRouter.scala b/src/main/scala/amba/apb/RegisterRouter.scala index 1cd52a63..3c136552 100644 --- a/src/main/scala/amba/apb/RegisterRouter.scala +++ b/src/main/scala/amba/apb/RegisterRouter.scala @@ -10,8 +10,8 @@ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.HeterogeneousBag import scala.math.{min,max} -class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) - extends APBSlaveNode(Seq(APBSlavePortParameters( +case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName) + extends SinkNode(APBImp)(Seq(APBSlavePortParameters( Seq(APBSlaveParameters( address = Seq(address), executable = executable, @@ -51,12 +51,6 @@ class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int } } -object APBRegisterNode -{ - def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) = - new APBRegisterNode(address, concurrency, beatBytes, undefZero, executable) -} - // These convenience methods below combine to make it possible to create a APB // register mapped device from a totally abstract register mapped device. diff --git a/src/main/scala/amba/axi4/Nodes.scala b/src/main/scala/amba/axi4/Nodes.scala index dacbefcc..8b68470c 100644 --- a/src/main/scala/amba/axi4/Nodes.scala +++ b/src/main/scala/amba/axi4/Nodes.scala @@ -26,22 +26,23 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters } // Nodes implemented inside modules -case class AXI4IdentityNode() extends IdentityNode(AXI4Imp) -case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters]) extends SourceNode(AXI4Imp)(portParams) -case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters]) extends SinkNode(AXI4Imp)(portParams) +case class AXI4IdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4Imp) +case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams) +case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams) case class AXI4AdapterNode( masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters, slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters, - numPorts: Range.Inclusive = 0 to 999) + numPorts: Range.Inclusive = 0 to 999)( + implicit valName: ValName) extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts) // Nodes passed from an inner module -case class AXI4OutputNode() extends OutputNode(AXI4Imp) -case class AXI4InputNode() extends InputNode(AXI4Imp) +case class AXI4OutputNode()(implicit valName: ValName) extends OutputNode(AXI4Imp) +case class AXI4InputNode()(implicit valName: ValName) extends InputNode(AXI4Imp) // Nodes used for external ports -case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends BlindOutputNode(AXI4Imp)(portParams) -case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters]) extends BlindInputNode(AXI4Imp)(portParams) +case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AXI4Imp)(portParams) +case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AXI4Imp)(portParams) -case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends InternalOutputNode(AXI4Imp)(portParams) -case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters]) extends InternalInputNode(AXI4Imp)(portParams) +case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AXI4Imp)(portParams) +case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AXI4Imp)(portParams) diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala index 20d431b0..9f9b3082 100644 --- a/src/main/scala/amba/axi4/RegisterRouter.scala +++ b/src/main/scala/amba/axi4/RegisterRouter.scala @@ -10,8 +10,8 @@ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.{HeterogeneousBag, MaskGen} import scala.math.{min,max} -class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) - extends AXI4SlaveNode(Seq(AXI4SlavePortParameters( +case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName) + extends SinkNode(AXI4Imp)(Seq(AXI4SlavePortParameters( Seq(AXI4SlaveParameters( address = Seq(address), executable = executable, @@ -77,12 +77,6 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int } } -object AXI4RegisterNode -{ - def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) = - new AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable) -} - // These convenience methods below combine to make it possible to create a AXI4 // register mapped device from a totally abstract register mapped device. diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala index 54610873..8d77556d 100644 --- a/src/main/scala/amba/axi4/ToTL.scala +++ b/src/main/scala/amba/axi4/ToTL.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)( +case class AXI4ToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case AXI4MasterPortParameters(masters, userBits) => masters.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") } val maxFlight = masters.map(_.maxFlight.get).max diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala index 7fc892e8..75c1f1a5 100644 --- a/src/main/scala/diplomacy/Nodes.scala +++ b/src/main/scala/diplomacy/Nodes.scala @@ -67,7 +67,7 @@ trait OutwardNodeImp[DO, UO, EO, BO <: Data] abstract class NodeImp[D, U, EO, EI, B <: Data] extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B] -abstract class BaseNode +abstract class BaseNode(implicit val valName: ValName) { require (!LazyModule.stack.isEmpty, "You cannot create a node outside a LazyModule!") @@ -178,7 +178,8 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( inner: InwardNodeImp [DI, UI, EI, BI], outer: OutwardNodeImp[DO, UO, EO, BO])( protected[diplomacy] val numPO: Range.Inclusive, - protected[diplomacy] val numPI: Range.Inclusive) + protected[diplomacy] val numPI: Range.Inclusive)( + implicit valName: ValName) extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) @@ -308,7 +309,8 @@ abstract class MixedCustomNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( inner: InwardNodeImp [DI, UI, EI, BI], outer: OutwardNodeImp[DO, UO, EO, BO])( numPO: Range.Inclusive, - numPI: Range.Inclusive) + numPI: Range.Inclusive)( + implicit valName: ValName) extends MixedNode(inner, outer)(numPO, numPI) { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) @@ -318,7 +320,8 @@ abstract class MixedCustomNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( abstract class CustomNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])( numPO: Range.Inclusive, - numPI: Range.Inclusive) + numPI: Range.Inclusive)( + implicit valName: ValName) extends MixedCustomNode(imp, imp)(numPO, numPI) class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( @@ -326,7 +329,8 @@ class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( outer: OutwardNodeImp[DO, UO, EO, BO])( dFn: DI => DO, uFn: UO => UI, - num: Range.Inclusive = 0 to 999) + num: Range.Inclusive = 0 to 999)( + implicit valName: ValName) extends MixedNode(inner, outer)(num, num) { val externalIn: Boolean = true @@ -358,7 +362,8 @@ class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( dFn: Seq[DI] => DO, uFn: Seq[UO] => UI, numPO: Range.Inclusive = 1 to 999, - numPI: Range.Inclusive = 1 to 999) + numPI: Range.Inclusive = 1 to 999)( + implicit valName: ValName) extends MixedNode(inner, outer)(numPO, numPI) { // require (numPO.end >= 1, s"${name} does not accept outputs${lazyModule.line}") @@ -379,14 +384,16 @@ class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( class AdapterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])( dFn: D => D, uFn: U => U, - num: Range.Inclusive = 0 to 999) + num: Range.Inclusive = 0 to 999)( + implicit valName: ValName) extends MixedAdapterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, num) class NexusNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])( dFn: Seq[D] => D, uFn: Seq[U] => U, numPO: Range.Inclusive = 1 to 999, - numPI: Range.Inclusive = 1 to 999) + numPI: Range.Inclusive = 1 to 999)( + implicit valName: ValName) extends MixedNexusNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI) case class SplitterArg[T](newSize: Int, ports: Seq[T]) @@ -396,7 +403,8 @@ class MixedSplitterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( dFn: SplitterArg[DI] => Seq[DO], uFn: SplitterArg[UO] => Seq[UI], numPO: Range.Inclusive = 1 to 999, - numPI: Range.Inclusive = 1 to 999) + numPI: Range.Inclusive = 1 to 999)( + implicit valName: ValName) extends MixedNode(inner, outer)(numPO, numPI) { override val externalIn: Boolean = true @@ -425,20 +433,21 @@ class SplitterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])( dFn: SplitterArg[D] => Seq[D], uFn: SplitterArg[U] => Seq[U], numPO: Range.Inclusive = 1 to 999, - numPI: Range.Inclusive = 1 to 999) + numPI: Range.Inclusive = 1 to 999)( + implicit valName: ValName) extends MixedSplitterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI) -class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) +class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends AdapterNode(imp)({s => s}, {s => s}) -class OutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends IdentityNode(imp) +class OutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends IdentityNode(imp) { override val externalIn: Boolean = false override val externalOut: Boolean = true override lazy val bundleIn = bundleOut } -class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends IdentityNode(imp) +class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends IdentityNode(imp) { override val externalIn: Boolean = true override val externalOut: Boolean = false @@ -446,7 +455,7 @@ class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends override lazy val bundleOut = bundleIn } -class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D]) +class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName) extends MixedNode(imp, imp)(po.size to po.size, 0 to 0) { override val externalIn: Boolean = false @@ -465,7 +474,7 @@ class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq override lazy val bundleIn = { require(false, s"${name} has no bundleIn; try bundleOut?"); bundleOut } } -class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U]) +class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName) extends MixedNode(imp, imp)(0 to 0, pi.size to pi.size) { override val externalIn: Boolean = true @@ -484,7 +493,7 @@ class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn } } -class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U]) +class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName) extends SinkNode(imp)(pi) { override val externalIn: Boolean = false @@ -492,7 +501,7 @@ class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi override lazy val bundleOut = bundleIn } -class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D]) +class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName) extends SourceNode(imp)(po) { override val externalOut: Boolean = false @@ -500,7 +509,7 @@ class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: override lazy val bundleIn = bundleOut } -class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U]) +class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName) extends SinkNode(imp)(pi) { override val externalIn: Boolean = false @@ -509,7 +518,7 @@ class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) override lazy val bundleOut = bundleIn } -class InternalInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D]) +class InternalInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName) extends SourceNode(imp)(po) { override val externalIn: Boolean = false diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index caa6f1a1..14d91e6f 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -244,7 +244,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) val masterNode = TLOutputNode() masterNode :=* optionalMasterBuffer(rocket.masterNode) - val slaveNode = new TLInputNode() { override def reverse = true } + val slaveNode = new TLInputNode()(ValName("slave")) { override def reverse = true } DisableMonitors { implicit p => rocket.slaveNode :*= optionalSlaveBuffer(slaveNode) } // Fully async interrupts need synchronizers. @@ -265,7 +265,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters source.node :=* rocket.masterNode masterNode :=* source.node - val slaveNode = new TLAsyncInputNode() { override def reverse = true } + val slaveNode = new TLAsyncInputNode()(ValName("slave")) { override def reverse = true } val sink = LazyModule(new TLAsyncCrossingSink) DisableMonitors { implicit p => @@ -294,7 +294,7 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet source.node :=* optionalMasterBuffer(rocket.masterNode) masterNode :=* source.node - val slaveNode = new TLRationalInputNode() { override def reverse = true } + val slaveNode = new TLRationalInputNode()(ValName("slave")) { override def reverse = true } val sink = LazyModule(new TLRationalCrossingSink(SlowToFast)) DisableMonitors { implicit p => diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala index 4ce803cc..6242a1a9 100644 --- a/src/main/scala/tilelink/Buffer.scala +++ b/src/main/scala/tilelink/Buffer.scala @@ -13,7 +13,7 @@ class TLBufferNode ( b: BufferParams, c: BufferParams, d: BufferParams, - e: BufferParams)(implicit p: Parameters) extends TLAdapterNode( + e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.copy(minLatency = p.minLatency + a.latency + d.latency) } ) { diff --git a/src/main/scala/tilelink/IntNodes.scala b/src/main/scala/tilelink/IntNodes.scala index 3b9cab83..c9deea7b 100644 --- a/src/main/scala/tilelink/IntNodes.scala +++ b/src/main/scala/tilelink/IntNodes.scala @@ -88,25 +88,26 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) }) } -case class IntIdentityNode() extends IdentityNode(IntImp) -case class IntSourceNode(portParams: Seq[IntSourcePortParameters]) extends SourceNode(IntImp)(portParams) -case class IntSinkNode(portParams: Seq[IntSinkPortParameters]) extends SinkNode(IntImp)(portParams) +case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp) +case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams) +case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams) case class IntNexusNode( sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters, sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters, numSourcePorts: Range.Inclusive = 0 to 128, - numSinkPorts: Range.Inclusive = 0 to 128) + numSinkPorts: Range.Inclusive = 0 to 128)( + implicit valName: ValName) extends NexusNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts) -case class IntOutputNode() extends OutputNode(IntImp) -case class IntInputNode() extends InputNode(IntImp) +case class IntOutputNode()(implicit valName: ValName) extends OutputNode(IntImp) +case class IntInputNode()(implicit valName: ValName) extends InputNode(IntImp) -case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters]) extends BlindOutputNode(IntImp)(portParams) -case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters]) extends BlindInputNode(IntImp)(portParams) +case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends BlindOutputNode(IntImp)(portParams) +case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends BlindInputNode(IntImp)(portParams) -case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters]) extends InternalOutputNode(IntImp)(portParams) -case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters]) extends InternalInputNode(IntImp)(portParams) +case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends InternalOutputNode(IntImp)(portParams) +case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends InternalInputNode(IntImp)(portParams) class IntXbar()(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/tilelink/NodeNumberer.scala b/src/main/scala/tilelink/NodeNumberer.scala index 1f7fa6f3..cee8508b 100644 --- a/src/main/scala/tilelink/NodeNumberer.scala +++ b/src/main/scala/tilelink/NodeNumberer.scala @@ -7,7 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ -case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None) extends TLCustomNode(0 to 999, 0 to 999) +case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None)(implicit valName: ValName) extends TLCustomNode(0 to 999, 0 to 999) { val externalIn = true val externalOut = true diff --git a/src/main/scala/tilelink/Nodes.scala b/src/main/scala/tilelink/Nodes.scala index 4d4912f4..273d9659 100644 --- a/src/main/scala/tilelink/Nodes.scala +++ b/src/main/scala/tilelink/Nodes.scala @@ -64,57 +64,61 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL } // Nodes implemented inside modules -case class TLIdentityNode() extends IdentityNode(TLImp) -case class TLClientNode(portParams: Seq[TLClientPortParameters]) extends SourceNode(TLImp)(portParams) -case class TLManagerNode(portParams: Seq[TLManagerPortParameters]) extends SinkNode(TLImp)(portParams) +case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp) +case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) +case class TLManagerNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) object TLClientNode { - def apply(params: TLClientParameters) = + def apply(params: TLClientParameters)(implicit valName: ValName) = new TLClientNode(Seq(TLClientPortParameters(Seq(params)))) } object TLManagerNode { - def apply(beatBytes: Int, params: TLManagerParameters) = + def apply(beatBytes: Int, params: TLManagerParameters)(implicit valName: ValName) = new TLManagerNode(Seq(TLManagerPortParameters(Seq(params), beatBytes, minLatency = 0))) } case class TLAdapterNode( clientFn: TLClientPortParameters => TLClientPortParameters, managerFn: TLManagerPortParameters => TLManagerPortParameters, - num: Range.Inclusive = 0 to 999) + num: Range.Inclusive = 0 to 999)( + implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn, num) case class TLNexusNode( clientFn: Seq[TLClientPortParameters] => TLClientPortParameters, managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters, numClientPorts: Range.Inclusive = 1 to 999, - numManagerPorts: Range.Inclusive = 1 to 999) + numManagerPorts: Range.Inclusive = 1 to 999)( + implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts) case class TLSplitterNode( clientFn: SplitterArg[TLClientPortParameters] => Seq[TLClientPortParameters], managerFn: SplitterArg[TLManagerPortParameters] => Seq[TLManagerPortParameters], numClientPorts: Range.Inclusive = 0 to 999, - numManagerPorts: Range.Inclusive = 0 to 999) + numManagerPorts: Range.Inclusive = 0 to 999)( + implicit valName: ValName) extends SplitterNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts) abstract class TLCustomNode( numClientPorts: Range.Inclusive, - numManagerPorts: Range.Inclusive) + numManagerPorts: Range.Inclusive)( + implicit valName: ValName) extends CustomNode(TLImp)(numClientPorts, numManagerPorts) // Nodes passed from an inner module -case class TLOutputNode() extends OutputNode(TLImp) -case class TLInputNode() extends InputNode(TLImp) +case class TLOutputNode()(implicit valName: ValName) extends OutputNode(TLImp) +case class TLInputNode()(implicit valName: ValName) extends InputNode(TLImp) // Nodes used for external ports -case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters]) extends BlindOutputNode(TLImp)(portParams) -case class TLBlindInputNode(portParams: Seq[TLClientPortParameters]) extends BlindInputNode(TLImp)(portParams) +case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends BlindOutputNode(TLImp)(portParams) +case class TLBlindInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends BlindInputNode(TLImp)(portParams) -case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters]) extends InternalOutputNode(TLImp)(portParams) -case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends InternalInputNode(TLImp)(portParams) +case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends InternalOutputNode(TLImp)(portParams) +case class TLInternalInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends InternalInputNode(TLImp)(portParams) /** Synthesizeable unit tests */ import freechips.rocketchip.unittest._ @@ -156,16 +160,16 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) })) } -case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp) -case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp) -case class TLAsyncInputNode() extends InputNode(TLAsyncImp) +case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp) +case class TLAsyncOutputNode()(implicit valName: ValName) extends OutputNode(TLAsyncImp) +case class TLAsyncInputNode()(implicit valName: ValName) extends InputNode(TLAsyncImp) -case class TLAsyncSourceNode(sync: Int) +case class TLAsyncSourceNode(sync: Int)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.copy(minLatency = sync+1) }) // discard cycles in other clock domain -case class TLAsyncSinkNode(depth: Int, sync: Int) +case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.copy(minLatency = sync+1) }, uFn = { p => TLAsyncManagerPortParameters(depth, p) }) @@ -186,16 +190,16 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) })) } -case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp) -case class TLRationalOutputNode() extends OutputNode(TLRationalImp) -case class TLRationalInputNode() extends InputNode(TLRationalImp) +case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp) +case class TLRationalOutputNode()(implicit valName: ValName) extends OutputNode(TLRationalImp) +case class TLRationalInputNode()(implicit valName: ValName) extends InputNode(TLRationalImp) -case class TLRationalSourceNode() +case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain -case class TLRationalSinkNode(direction: RationalDirection) +case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala index 4c2c52df..5ecd5398 100644 --- a/src/main/scala/tilelink/RegisterRouter.scala +++ b/src/main/scala/tilelink/RegisterRouter.scala @@ -9,15 +9,16 @@ import freechips.rocketchip.regmapper._ import freechips.rocketchip.util.HeterogeneousBag import scala.math.{min,max} -class TLRegisterNode( +case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, - executable: Boolean = false) - extends TLManagerNode(Seq(TLManagerPortParameters( + executable: Boolean = false)( + implicit valName: ValName) + extends SinkNode(TLImp)(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = address, resources = Seq(Resource(device, deviceKey)), @@ -81,20 +82,6 @@ class TLRegisterNode( } } -object TLRegisterNode -{ - def apply( - address: Seq[AddressSet], - device: Device, - deviceKey: String = "reg/control", - concurrency: Int = 0, - beatBytes: Int = 4, - undefZero: Boolean = true, - executable: Boolean = false) = - new TLRegisterNode(address, device, deviceKey, concurrency, beatBytes, undefZero, executable) -} - -// These convenience methods below combine to make it possible to create a TL2 // register mapped device from a totally abstract register mapped device. // See GPIO.scala in this directory for an example diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala index cadae46e..bf61964d 100644 --- a/src/main/scala/tilelink/ToAHB.scala +++ b/src/main/scala/tilelink/ToAHB.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.util._ import scala.math.{min, max} import AHBParameters._ -case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)( +case class TLToAHBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImp)( dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) => val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) } AHBMasterPortParameters(masters) diff --git a/src/main/scala/tilelink/ToAPB.scala b/src/main/scala/tilelink/ToAPB.scala index 2d0bf2ae..e6ed742a 100644 --- a/src/main/scala/tilelink/ToAPB.scala +++ b/src/main/scala/tilelink/ToAPB.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.amba.apb._ import scala.math.{min, max} import APBParameters._ -case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)( +case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)( dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) => val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) } APBMasterPortParameters(masters) diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala index a4588006..21385abb 100644 --- a/src/main/scala/tilelink/ToAXI4.scala +++ b/src/main/scala/tilelink/ToAXI4.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.amba.axi4._ import scala.math.{min, max} -case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0) extends MixedAdapterNode(TLImp, AXI4Imp)( +case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => p.clients.foreach { c => require (c.sourceId.start % (1 << stripBits) == 0 &&