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nodes: grab a name on construction

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This commit is contained in:
Wesley W. Terpstra
2017-09-11 23:33:44 -07:00
parent 3656e975a1
commit d89ee9d9d4
18 changed files with 121 additions and 135 deletions
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2
src/main/scala/tilelink/Buffer.scala
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@ -13,7 +13,7 @@ class TLBufferNode (
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends TLAdapterNode(
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.copy(minLatency = p.minLatency + a.latency + d.latency) }
) {

21
src/main/scala/tilelink/IntNodes.scala
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@ -88,25 +88,26 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
}
case class IntIdentityNode() extends IdentityNode(IntImp)
case class IntSourceNode(portParams: Seq[IntSourcePortParameters]) extends SourceNode(IntImp)(portParams)
case class IntSinkNode(portParams: Seq[IntSinkPortParameters]) extends SinkNode(IntImp)(portParams)
case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)
case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams)
case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams)
case class IntNexusNode(
sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters,
numSourcePorts: Range.Inclusive = 0 to 128,
numSinkPorts: Range.Inclusive = 0 to 128)
numSinkPorts: Range.Inclusive = 0 to 128)(
implicit valName: ValName)
extends NexusNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
case class IntOutputNode() extends OutputNode(IntImp)
case class IntInputNode() extends InputNode(IntImp)
case class IntOutputNode()(implicit valName: ValName) extends OutputNode(IntImp)
case class IntInputNode()(implicit valName: ValName) extends InputNode(IntImp)
case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters]) extends BlindOutputNode(IntImp)(portParams)
case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters]) extends BlindInputNode(IntImp)(portParams)
case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends BlindOutputNode(IntImp)(portParams)
case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends BlindInputNode(IntImp)(portParams)
case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters]) extends InternalOutputNode(IntImp)(portParams)
case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters]) extends InternalInputNode(IntImp)(portParams)
case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends InternalOutputNode(IntImp)(portParams)
case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends InternalInputNode(IntImp)(portParams)
class IntXbar()(implicit p: Parameters) extends LazyModule
{

2
src/main/scala/tilelink/NodeNumberer.scala
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@ -7,7 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None) extends TLCustomNode(0 to 999, 0 to 999)
case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None)(implicit valName: ValName) extends TLCustomNode(0 to 999, 0 to 999)
{
val externalIn = true
val externalOut = true

54
src/main/scala/tilelink/Nodes.scala
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@ -64,57 +64,61 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
}
// Nodes implemented inside modules
case class TLIdentityNode() extends IdentityNode(TLImp)
case class TLClientNode(portParams: Seq[TLClientPortParameters]) extends SourceNode(TLImp)(portParams)
case class TLManagerNode(portParams: Seq[TLManagerPortParameters]) extends SinkNode(TLImp)(portParams)
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)
case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams)
case class TLManagerNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams)
object TLClientNode
{
def apply(params: TLClientParameters) =
def apply(params: TLClientParameters)(implicit valName: ValName) =
new TLClientNode(Seq(TLClientPortParameters(Seq(params))))
}
object TLManagerNode
{
def apply(beatBytes: Int, params: TLManagerParameters) =
def apply(beatBytes: Int, params: TLManagerParameters)(implicit valName: ValName) =
new TLManagerNode(Seq(TLManagerPortParameters(Seq(params), beatBytes, minLatency = 0)))
}
case class TLAdapterNode(
clientFn: TLClientPortParameters => TLClientPortParameters,
managerFn: TLManagerPortParameters => TLManagerPortParameters,
num: Range.Inclusive = 0 to 999)
num: Range.Inclusive = 0 to 999)(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn, num)
case class TLNexusNode(
clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
numClientPorts: Range.Inclusive = 1 to 999,
numManagerPorts: Range.Inclusive = 1 to 999)
numManagerPorts: Range.Inclusive = 1 to 999)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
case class TLSplitterNode(
clientFn: SplitterArg[TLClientPortParameters] => Seq[TLClientPortParameters],
managerFn: SplitterArg[TLManagerPortParameters] => Seq[TLManagerPortParameters],
numClientPorts: Range.Inclusive = 0 to 999,
numManagerPorts: Range.Inclusive = 0 to 999)
numManagerPorts: Range.Inclusive = 0 to 999)(
implicit valName: ValName)
extends SplitterNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
abstract class TLCustomNode(
numClientPorts: Range.Inclusive,
numManagerPorts: Range.Inclusive)
numManagerPorts: Range.Inclusive)(
implicit valName: ValName)
extends CustomNode(TLImp)(numClientPorts, numManagerPorts)
// Nodes passed from an inner module
case class TLOutputNode() extends OutputNode(TLImp)
case class TLInputNode() extends InputNode(TLImp)
case class TLOutputNode()(implicit valName: ValName) extends OutputNode(TLImp)
case class TLInputNode()(implicit valName: ValName) extends InputNode(TLImp)
// Nodes used for external ports
case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters]) extends BlindOutputNode(TLImp)(portParams)
case class TLBlindInputNode(portParams: Seq[TLClientPortParameters]) extends BlindInputNode(TLImp)(portParams)
case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends BlindOutputNode(TLImp)(portParams)
case class TLBlindInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends BlindInputNode(TLImp)(portParams)
case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters]) extends InternalOutputNode(TLImp)(portParams)
case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends InternalInputNode(TLImp)(portParams)
case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends InternalOutputNode(TLImp)(portParams)
case class TLInternalInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends InternalInputNode(TLImp)(portParams)
/** Synthesizeable unit tests */
import freechips.rocketchip.unittest._
@ -156,16 +160,16 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)
case class TLAsyncOutputNode()(implicit valName: ValName) extends OutputNode(TLAsyncImp)
case class TLAsyncInputNode()(implicit valName: ValName) extends InputNode(TLAsyncImp)
case class TLAsyncSourceNode(sync: Int)
case class TLAsyncSourceNode(sync: Int)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.copy(minLatency = sync+1) }) // discard cycles in other clock domain
case class TLAsyncSinkNode(depth: Int, sync: Int)
case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.copy(minLatency = sync+1) },
uFn = { p => TLAsyncManagerPortParameters(depth, p) })
@ -186,16 +190,16 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp)
case class TLRationalOutputNode() extends OutputNode(TLRationalImp)
case class TLRationalInputNode() extends InputNode(TLRationalImp)
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)
case class TLRationalOutputNode()(implicit valName: ValName) extends OutputNode(TLRationalImp)
case class TLRationalInputNode()(implicit valName: ValName) extends InputNode(TLRationalImp)
case class TLRationalSourceNode()
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) })

21
src/main/scala/tilelink/RegisterRouter.scala
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@ -9,15 +9,16 @@ import freechips.rocketchip.regmapper._
import freechips.rocketchip.util.HeterogeneousBag
import scala.math.{min,max}
class TLRegisterNode(
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)
extends TLManagerNode(Seq(TLManagerPortParameters(
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = address,
resources = Seq(Resource(device, deviceKey)),
@ -81,20 +82,6 @@ class TLRegisterNode(
}
}
object TLRegisterNode
{
def apply(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false) =
new TLRegisterNode(address, device, deviceKey, concurrency, beatBytes, undefZero, executable)
}
// These convenience methods below combine to make it possible to create a TL2
// register mapped device from a totally abstract register mapped device.
// See GPIO.scala in this directory for an example

2
src/main/scala/tilelink/ToAHB.scala
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@ -11,7 +11,7 @@ import freechips.rocketchip.util._
import scala.math.{min, max}
import AHBParameters._
case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
case class TLToAHBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImp)(
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
AHBMasterPortParameters(masters)

2
src/main/scala/tilelink/ToAPB.scala
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@ -10,7 +10,7 @@ import freechips.rocketchip.amba.apb._
import scala.math.{min, max}
import APBParameters._
case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)(
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
APBMasterPortParameters(masters)

2
src/main/scala/tilelink/ToAXI4.scala
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@ -10,7 +10,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.amba.axi4._
import scala.math.{min, max}
case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0) extends MixedAdapterNode(TLImp, AXI4Imp)(
case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
dFn = { p =>
p.clients.foreach { c =>
require (c.sourceId.start % (1 << stripBits) == 0 &&