riscv/rocket-chip
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nodes: grab a name on construction

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This commit is contained in:
Wesley W. Terpstra
2017-09-11 23:33:44 -07:00
parent 3656e975a1
commit d89ee9d9d4
18 changed files with 121 additions and 135 deletions
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6
src/main/scala/tile/RocketTile.scala
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@@ -244,7 +244,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
val masterNode = TLOutputNode()
masterNode :=* optionalMasterBuffer(rocket.masterNode)
val slaveNode = new TLInputNode() { override def reverse = true }
val slaveNode = new TLInputNode()(ValName("slave")) { override def reverse = true }
DisableMonitors { implicit p => rocket.slaveNode :*= optionalSlaveBuffer(slaveNode) }
// Fully async interrupts need synchronizers.
@@ -265,7 +265,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
source.node :=* rocket.masterNode
masterNode :=* source.node
val slaveNode = new TLAsyncInputNode() { override def reverse = true }
val slaveNode = new TLAsyncInputNode()(ValName("slave")) { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink)
DisableMonitors { implicit p =>
@@ -294,7 +294,7 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
source.node :=* optionalMasterBuffer(rocket.masterNode)
masterNode :=* source.node
val slaveNode = new TLRationalInputNode() { override def reverse = true }
val slaveNode = new TLRationalInputNode()(ValName("slave")) { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
DisableMonitors { implicit p =>