riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

RegFieldDesc: add volatile to cause reg in BUE

Browse Source
This commit is contained in:
Megan Wachs 2018-03-09 17:20:38 -08:00
parent e0c3c63826
commit d889a0ca16
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/BusErrorUnit.scala
View File

@ -54,7 +54,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
val causeWidth = log2Ceil(sources.lastIndexWhere(_.nonEmpty) + 1) val causeWidth = log2Ceil(sources.lastIndexWhere(_.nonEmpty) + 1)
val (cause, cause_desc) = DescribedReg(UInt(causeWidth.W), val (cause, cause_desc) = DescribedReg(UInt(causeWidth.W),
"cause", "Cause of error event", reset=Some(0.U(causeWidth.W)), enumerations=sources_enums.toMap) "cause", "Cause of error event", reset=Some(0.U(causeWidth.W)), volatile=true, enumerations=sources_enums.toMap)
val (value, value_desc) = DescribedReg(UInt(width = sources.flatten.map(_.bits.getWidth).max), val (value, value_desc) = DescribedReg(UInt(width = sources.flatten.map(_.bits.getWidth).max),
"value", "Physical address of error event", reset=None, volatile=true) "value", "Physical address of error event", reset=None, volatile=true)