From d889a0ca16550ee18a9a65fc14d6f359239d503c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 9 Mar 2018 17:20:38 -0800 Subject: [PATCH] RegFieldDesc: add volatile to cause reg in BUE --- src/main/scala/rocket/BusErrorUnit.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/BusErrorUnit.scala b/src/main/scala/rocket/BusErrorUnit.scala index 838e98b7..54f47d6d 100644 --- a/src/main/scala/rocket/BusErrorUnit.scala +++ b/src/main/scala/rocket/BusErrorUnit.scala @@ -54,7 +54,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit val causeWidth = log2Ceil(sources.lastIndexWhere(_.nonEmpty) + 1) val (cause, cause_desc) = DescribedReg(UInt(causeWidth.W), - "cause", "Cause of error event", reset=Some(0.U(causeWidth.W)), enumerations=sources_enums.toMap) + "cause", "Cause of error event", reset=Some(0.U(causeWidth.W)), volatile=true, enumerations=sources_enums.toMap) val (value, value_desc) = DescribedReg(UInt(width = sources.flatten.map(_.bits.getWidth).max), "value", "Physical address of error event", reset=None, volatile=true)