riscv/rocket-chip
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properly shift grant data when checking correctness

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This commit is contained in:
Howard Mao 2015-10-31 18:58:05 -07:00
parent 644b66a3a8
commit d844bee310
1 changed files with 7 additions and 1 deletions
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8
groundtest/src/main/scala/generator.scala
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@ -93,8 +93,14 @@ class UncachedTileLinkGenerator(id: Int)
io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
io.mem.grant.ready := !sending
def wordFromBeat(addr: UInt, dat: UInt) = {
val offset = addr(tlByteAddrBits - 1, wordOffset)
val shift = Cat(offset, UInt(0, wordOffset + 3))
(dat >> shift)(wordBits - 1, 0)
}
assert(!io.mem.grant.valid || state =/= s_get ||
io.mem.grant.bits.data(63, 0) === word_data,
wordFromBeat(full_addr, io.mem.grant.bits.data) === word_data,
s"Get received incorrect data in uncached generator ${id}")
}