properly shift grant data when checking correctness
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@ -93,8 +93,14 @@ class UncachedTileLinkGenerator(id: Int)
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.mem.grant.ready := !sending
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io.mem.grant.ready := !sending
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def wordFromBeat(addr: UInt, dat: UInt) = {
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val offset = addr(tlByteAddrBits - 1, wordOffset)
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val shift = Cat(offset, UInt(0, wordOffset + 3))
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(dat >> shift)(wordBits - 1, 0)
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}
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assert(!io.mem.grant.valid || state =/= s_get ||
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assert(!io.mem.grant.valid || state =/= s_get ||
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io.mem.grant.bits.data(63, 0) === word_data,
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wordFromBeat(full_addr, io.mem.grant.bits.data) === word_data,
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s"Get received incorrect data in uncached generator ${id}")
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s"Get received incorrect data in uncached generator ${id}")
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}
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}
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