make NastiConverterTest act as generator and share blocks
This commit is contained in:
Howard Mao
parent
850fa092a4
commit
d80c2f480f
@ -6,93 +6,48 @@ import uncore.converters._
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import junctions._
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import cde.Parameters
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abstract class NastiTest(implicit val p: Parameters) extends Module
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with HasNastiParameters with HasMIFParameters with HasAddrMapParameters {
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class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module
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with HasNastiParameters
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with HasMIFParameters
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with HasAddrMapParameters
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with HasGeneratorParameters {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new NastiIO
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}
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val memStart = addrMap("mem").start + 0x40000
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}
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class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
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val (s_start :: s_write_req :: s_write_resp ::
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s_read_req :: s_read_resp :: s_finish :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_start)
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val addr_sent = Reg(init = Bool(false))
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val data_sent = Reg(init = UInt(0, mifDataBeats))
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val data_beats = Vec.tabulate(mifDataBeats) { i => UInt(i * 0x20) }
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val (r_count, r_done) = Counter(io.mem.r.fire(), mifDataBeats)
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val (w_count, w_done) = Counter(io.mem.w.fire(), mifDataBeats)
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io.mem.aw.valid := (state === s_write_req) && !addr_sent
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(memStart),
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len = UInt(mifDataBeats - 1),
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size = UInt(log2Up(mifDataBits / 8)))
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io.mem.w.valid := (state === s_write_req) && !data_sent.andR
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io.mem.w.bits := NastiWriteDataChannel(
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data = data_beats(w_count),
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last = w_count === UInt(mifDataBeats - 1))
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io.mem.b.ready := (state === s_write_resp)
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io.mem.ar.valid := (state === s_read_req)
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io.mem.ar.bits := NastiReadAddressChannel(
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id = UInt(1),
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addr = UInt(memStart),
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len = UInt(mifDataBeats - 1),
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size = UInt(log2Up(mifDataBits / 8)))
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io.mem.r.ready := (state === s_read_resp)
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when (state === s_start) { state := s_write_req }
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when (io.mem.aw.fire()) { addr_sent := Bool(true) }
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when (io.mem.w.fire()) { data_sent := data_sent | UIntToOH(w_count) }
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when (w_done) { state := s_write_resp }
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when (io.mem.b.fire()) { state := s_read_req }
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when (io.mem.ar.fire()) { state := s_read_resp }
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when (r_done) { state := s_finish }
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io.finished := (state === s_finish)
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assert(!io.mem.r.valid || io.mem.r.bits.data === data_beats(r_count),
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"NASTI Block Test: results do not match")
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}
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class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
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val mifDataBytes = mifDataBits / 8
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val (s_start :: s_write_addr :: s_write_data ::
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s_read :: s_wait :: s_finish :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_start)
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val nTests = 512
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val ref_data = Vec.tabulate(nTests) { i => UInt(0x35abffcd + i, 32) }
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def ref_data(idx: UInt) = UInt(0x35abffcd, genWordBits) + (idx << UInt(3))
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val (write_idx, write_done) = Counter(io.mem.w.fire(), nTests)
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val write_addr = UInt(memStart + 0x200) + Cat(write_idx, UInt(0, 2))
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val write_data = Fill(mifDataBits / 32, ref_data(write_idx))
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val part_of_addr =
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if (log2Ceil(nGens) > 0) {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(0, wordOffset))
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} else {
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UInt(0, wordOffset)
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}
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val (write_idx, write_done) = Counter(io.mem.w.fire(), maxRequests)
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val write_addr = UInt(startAddress) + Cat(write_idx, part_of_addr)
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val write_data = Fill(mifDataBits / genWordBits, ref_data(write_idx))
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val write_align = write_addr(log2Up(mifDataBytes) - 1, 0)
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val write_mask = UInt("h0f") << write_align
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val write_mask = UInt((1 << genWordBytes) - 1, nastiWStrobeBits) << write_align
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val (read_idx, read_done) = Counter(io.mem.ar.fire(), nTests)
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val read_addr = UInt(memStart + 0x200) + Cat(read_idx, UInt(0, 2))
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val (read_resp_idx, read_resp_done) = Counter(io.mem.r.fire(), nTests)
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val (read_idx, read_done) = Counter(io.mem.ar.fire(), maxRequests)
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val read_addr = UInt(startAddress) + Cat(read_idx, part_of_addr)
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io.mem.aw.valid := (state === s_write_addr)
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = write_addr,
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len = UInt(0),
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size = UInt("b010"))
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size = UInt(log2Ceil(genWordBytes)))
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io.mem.w.valid := (state === s_write_data)
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io.mem.w.bits := NastiWriteDataChannel(
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@ -105,11 +60,22 @@ class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
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id = UInt(0),
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addr = read_addr,
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len = UInt(0),
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size = UInt("b010"))
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size = UInt(log2Ceil(genWordBytes)))
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io.mem.r.ready := Bool(true)
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io.mem.b.ready := Bool(true)
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io.finished := (state === s_finish)
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val (read_resp_idx, read_resp_done) = Counter(io.mem.r.fire(), maxRequests)
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val read_resp_addr = UInt(startAddress) + Cat(read_resp_idx, part_of_addr)
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val read_offset = read_resp_addr(log2Up(nastiXDataBits / 8) - 1, 0)
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val read_shift = Cat(read_offset, UInt(0, 3))
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val read_data = (io.mem.r.bits.data >> read_shift)(genWordBits - 1, 0)
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assert(!io.mem.r.valid || read_data === ref_data(read_resp_idx),
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"NASTI Test: results do not match")
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when (state === s_start) { state := s_write_addr }
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when (io.mem.aw.fire()) { state := s_write_data }
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when (io.mem.w.fire()) { state := s_write_addr }
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@ -117,81 +83,34 @@ class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
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when (read_done) { state := s_wait }
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when (read_resp_done) { state := s_finish }
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io.finished := (state === s_finish)
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val readShiftBits = log2Ceil(mifDataBits / 32)
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val read_shift = Cat(read_resp_idx(readShiftBits - 1, 0), UInt(0, 5))
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val read_data = (io.mem.r.bits.data >> read_shift)(31, 0)
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assert(!io.mem.r.valid || read_data === ref_data(read_resp_idx),
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"NASTI Small Test: results do not match")
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}
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class NastiSequencer(n: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val in = Vec(n, new NastiIO).flip
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val out = new NastiIO()
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val finished = Vec(n, Bool(INPUT))
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}
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val selection = Reg(init = UInt(0, log2Up(n)))
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val all_finished = io.finished.reduce(_ && _)
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when (!all_finished && io.finished(selection)) {
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selection := selection + UInt(1)
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}
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io.out.ar.valid := io.in(selection).ar.valid
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io.out.ar.bits := io.in(selection).ar.bits
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io.out.aw.valid := io.in(selection).aw.valid
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io.out.aw.bits := io.in(selection).aw.bits
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io.out.w.valid := io.in(selection).w.valid
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io.out.w.bits := io.in(selection).w.bits
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io.out.b.ready := io.in(selection).b.ready
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io.out.r.ready := io.in(selection).r.ready
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for ((in, i) <- io.in.zipWithIndex) {
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val me = selection === UInt(i)
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in.ar.ready := io.out.ar.ready && me
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in.aw.ready := io.out.aw.ready && me
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in.w.ready := io.out.w.ready && me
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in.b.valid := io.out.b.valid && me
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in.b.bits := io.out.b.bits
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in.r.valid := io.out.r.valid && me
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in.r.bits := io.out.r.bits
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}
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val r_timer = Module(new Timer(1000, 2))
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r_timer.io.start.valid := io.out.ar.fire()
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r_timer.io.start.bits := io.out.ar.bits.id
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r_timer.io.stop.valid := io.out.r.fire() && io.out.r.bits.last
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r_timer.io.stop.bits := io.out.r.bits.id
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r_timer.io.start.valid := io.mem.ar.fire()
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r_timer.io.start.bits := io.mem.ar.bits.id
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r_timer.io.stop.valid := io.mem.r.fire() && io.mem.r.bits.last
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r_timer.io.stop.bits := io.mem.r.bits.id
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assert(!r_timer.io.timeout, "NASTI Read timed out")
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val w_timer = Module(new Timer(1000, 2))
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w_timer.io.start.valid := io.out.aw.fire()
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w_timer.io.start.bits := io.out.aw.bits.id
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w_timer.io.stop.valid := io.out.b.fire()
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w_timer.io.stop.bits := io.out.b.bits.id
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w_timer.io.start.valid := io.mem.aw.fire()
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w_timer.io.start.bits := io.mem.aw.bits.id
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w_timer.io.stop.valid := io.mem.b.fire()
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w_timer.io.stop.bits := io.mem.b.bits.id
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assert(!w_timer.io.timeout, "NASTI Write timed out")
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}
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class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
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with HasNastiParameters {
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val tests = Seq(Module(new NastiBlockTest), Module(new NastiSmallTest))
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require(tileSettings.uncached == 1 && tileSettings.cached == 0)
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val sequencer = Module(new NastiSequencer(tests.size))
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val genId = p(GroundTestKey).take(tileId)
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.map(settings => settings.cached + settings.uncached)
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.foldLeft(0)(_ + _)
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val test = Module(new NastiGenerator(genId))
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val converter = Module(new TileLinkIONastiIOConverter()(
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p.alterPartial { case TLId => "Outermost" }))
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sequencer.io.in <> tests.map(_.io.mem)
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sequencer.io.finished := tests.map(_.io.finished)
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converter.io.nasti <> sequencer.io.out
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converter.io.nasti <> test.io.mem
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TileLinkWidthAdapter(io.mem.head, converter.io.tl)
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io.finished := tests.map(_.io.finished).reduce(_ && _)
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io.finished := test.io.finished
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}
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