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tilelink2 Fragmenter: Mask low bits of D channel addr_lo

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This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
This commit is contained in:
Albert Ou 2016-09-22 12:36:28 -07:00 committed by Albert Ou
parent cd96a66ba6
commit d76b762657
1 changed files with 1 additions and 0 deletions
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src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -168,6 +168,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.addr_lo := out.d.bits.addr_lo & ~dsizeOH1
in.d.bits.source := out.d.bits.source >> fragmentBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)