From d76b7626574f451fb9f27240dabb872861b81c6c Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 22 Sep 2016 12:36:28 -0700 Subject: [PATCH] tilelink2 Fragmenter: Mask low bits of D channel addr_lo This fixes an issue where passing addr_lo through unchanged triggered unaligned address assertions in the Monitor. --- src/main/scala/uncore/tilelink2/Fragmenter.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 6c339255..43d73ab0 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -168,6 +168,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged + in.d.bits.addr_lo := out.d.bits.addr_lo & ~dsizeOH1 in.d.bits.source := out.d.bits.source >> fragmentBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)