riscv/rocket-chip
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RocketTile: make sure 'hartid' is available for traits (#1037)

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Wesley W. Terpstra 2017-10-09 21:03:18 -07:00 committed by GitHub
parent a9686ab883
commit d6766a8c68
1 changed files with 4 additions and 3 deletions
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5
src/main/scala/tile/RocketTile.scala
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@ -29,7 +29,9 @@ case class RocketTileParams(
require(dcache.isDefined)
}
class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
abstract class HartedTile(tileParams: TileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(tileParams)(p)
class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends HartedTile(rocketParams, rocketParams.hartid)(p)
with HasExternalInterrupts
with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
@ -40,7 +42,6 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
private def ofStr(x: String) = Seq(ResourceString(x))
private def ofRef(x: Device) = Seq(ResourceReference(x.label))
val hartid = rocketParams.hartid
val cpuDevice = new Device {
def describe(resources: ResourceBindings): Description = {
val block = p(CacheBlockBytes)