From d6766a8c68529fd1511fc93f27e327ea773e2939 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 9 Oct 2017 21:03:18 -0700 Subject: [PATCH] RocketTile: make sure 'hartid' is available for traits (#1037) --- src/main/scala/tile/RocketTile.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 6fec665f..89eda305 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -28,8 +28,10 @@ case class RocketTileParams( require(icache.isDefined) require(dcache.isDefined) } - -class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p) + +abstract class HartedTile(tileParams: TileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(tileParams)(p) + +class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends HartedTile(rocketParams, rocketParams.hartid)(p) with HasExternalInterrupts with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend @@ -40,7 +42,6 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext private def ofStr(x: String) = Seq(ResourceString(x)) private def ofRef(x: Device) = Seq(ResourceReference(x.label)) - val hartid = rocketParams.hartid val cpuDevice = new Device { def describe(resources: ResourceBindings): Description = { val block = p(CacheBlockBytes)