Merge pull request #914 from freechipsproject/critical-paths
Fix some critical paths
This commit is contained in:
Andrew Waterman
GitHub
commit
d66e8f8e80
@ -89,7 +89,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0
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val tl_out_a = Wire(tl_out.a)
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tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true))
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tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true))
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val tl_out_c = Wire(tl_out.c)
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tl_out.c <> (if (cacheParams.acquireBeforeRelease) Queue(tl_out_c, cacheDataBeats, flow = true) else tl_out_c)
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@ -184,8 +184,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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.reduce (_|_))
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(s1_meta_hit_way, s1_meta_hit_state, s1_meta, s1_meta_uncorrected(s1_victim_way))
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}
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val s1_data_way = Mux(inWriteback, releaseWay, s1_hit_way)
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val s1_data = Mux1H(s1_data_way, data.io.resp) // retime into s2 if critical
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val s1_data_way = Wire(init = Mux(inWriteback, releaseWay, s1_hit_way))
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val s1_all_data_ways = Vec(data.io.resp :+ dummyEncodeData(tl_out.d.bits.data))
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val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).mask)
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val s2_valid = Reg(next=s1_valid_masked && !s1_sfence, init=Bool(false)) && !io.cpu.s2_xcpt.asUInt.orR
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@ -210,7 +210,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s2_meta_errors = s2_meta.map(_.error).asUInt
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val s2_meta_error = s2_meta_errors.orR
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val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error
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val s2_data = RegEnable(s1_data, s1_valid || inWriteback)
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val s2_data = {
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val en = s1_valid || inWriteback || tl_out.d.fire()
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if (cacheParams.pipelineWayMux && nWays > 1) {
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val s2_data_way = RegEnable(s1_data_way, en)
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val s2_all_data_ways = (0 to nWays).map(i => RegEnable(s1_all_data_ways(i), en && s1_data_way(i)))
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Mux1H(s2_data_way, s2_all_data_ways)
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} else {
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RegEnable(Mux1H(s1_data_way, s1_all_data_ways), en)
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}
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}
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val s2_probe_way = RegEnable(s1_hit_way, s1_probe)
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val s2_probe_state = RegEnable(s1_hit_state, s1_probe)
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val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked)
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@ -417,7 +426,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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}
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when (grantIsUncachedData) {
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s2_data := dummyEncodeData(tl_out.d.bits.data)
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s1_data_way := 1.U << nWays
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s2_req.cmd := M_XRD
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s2_req.typ := req.typ
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s2_req.tag := req.tag
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@ -97,7 +97,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val s2_speculative = Reg(init=Bool(false))
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val s2_partial_insn_valid = RegInit(false.B)
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val s2_partial_insn = Reg(UInt(width = coreInstBits))
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val s2_wrong_path = Reg(Bool())
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val wrong_path = Reg(Bool())
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val s1_base_pc = ~(~s1_pc | (fetchBytes - 1))
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val ntpc = s1_base_pc + fetchBytes.U
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@ -180,11 +180,12 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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Mux(returnAddrLSBs(log2Ceil(fetchWidth)), ntpc, s1_base_pc | ((returnAddrLSBs << log2Ceil(coreInstBytes)) & (fetchBytes - 1)))
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btb.io.ras_update.bits.cfiType := btb.io.resp.bits.cfiType
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btb.io.ras_update.bits.prediction.valid := true
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} else when (fq.io.enq.fire()) {
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} else {
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val s2_btb_hit = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_base_pc = ~(~s2_pc | (fetchBytes-1))
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val taken_idx = Wire(UInt())
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val after_idx = Wire(UInt())
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val useRAS = Wire(init=false.B)
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def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
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val prevRVI = prevValid && prevBits(1,0) === 3
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@ -200,49 +201,57 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
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val rvcJAL = Bool(xLen == 32) && bits === Instructions.C_JAL
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val rvcJump = bits === Instructions.C_J || rvcJAL
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val rvcImm = Mux(bits(14), new RVCDecoder(bits).bImm.asSInt, 0.S) | Mux(bits(14,13) === 1, new RVCDecoder(bits).jImm.asSInt, 0.S)
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val rvcImm = Mux(bits(14), new RVCDecoder(bits).bImm.asSInt, new RVCDecoder(bits).jImm.asSInt)
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val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0
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val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
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val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0
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val rvcCall = rvcJAL || rvcJALR
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val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), 0.S) | Mux(!rviBits(2), ImmGen(IMM_SB, rviBits), 0.S)
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val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits))
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val taken =
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prevRVI && (rviJump || rviJALR || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && s2_btb_resp_bits.bht.taken)
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val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
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val predictBranch =
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prevRVI && (rviJump || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcBranch && s2_btb_resp_bits.bht.taken)
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when (!prevTaken) {
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taken_idx := idx
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after_idx := idx + 1
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btb.io.ras_update.valid := !s2_wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
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btb.io.ras_update.valid := fq.io.enq.fire() && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
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btb.io.ras_update.bits.prediction.valid := true
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btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, CFIType.call)
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when (!s2_btb_hit) {
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when (prevRVI && (rviJALR && !(rviReturn && btb.io.ras_head.valid)) ||
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valid && (rvcJALR || (rvcJR && !btb.io.ras_head.valid))) {
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s2_wrong_path := true
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when (fq.io.enq.fire() && taken && !predictBranch && !predictReturn) {
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wrong_path := true
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}
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when (taken) {
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when (s2_valid && predictReturn) {
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useRAS := true
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}
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when (s2_valid && predictBranch) {
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val pc = s2_base_pc | (idx*coreInstBytes)
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val npc =
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if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
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else Mux(prevRVI, pc - coreInstBytes, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
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predicted_npc := Mux(prevRVI && rviReturn || valid && rvcReturn, btb.io.ras_head.bits, npc.asUInt)
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predicted_npc := npc.asUInt
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}
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when (prevRVI && rviBranch || valid && rvcBranch) {
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btb.io.bht_advance.valid := !s2_wrong_path && !s2_btb_resp_valid
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btb.io.bht_advance.valid := fq.io.enq.fire() && !wrong_path && !s2_btb_resp_valid
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btb.io.bht_advance.bits := s2_btb_resp_bits
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}
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}
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}
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if (idx == fetchWidth-1) {
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when (fq.io.enq.fire()) {
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s2_partial_insn_valid := false
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when (valid && !prevTaken && !rvc) {
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s2_partial_insn_valid := true
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s2_partial_insn := bits | 0x3
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}
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}
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prevTaken || taken
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} else {
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scanInsns(idx + 1, valid, bits, prevTaken || taken)
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@ -252,20 +261,24 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
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val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
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when (s2_btb_hit) {
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when (useRAS) {
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predicted_npc := btb.io.ras_head.bits
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}
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when (fq.io.enq.fire() && s2_btb_hit) {
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s2_partial_insn_valid := false
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}.otherwise {
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}
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when (!s2_btb_hit) {
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fq.io.enq.bits.btb.bits.bridx := taken_idx
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when (taken) {
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fq.io.enq.bits.btb.valid := true
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fq.io.enq.bits.btb.bits.taken := true
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fq.io.enq.bits.btb.bits.entry := UInt(tileParams.btb.get.nEntries)
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s2_redirect := true
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when (fq.io.enq.fire()) { s2_redirect := true }
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}
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}
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}
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when (s2_redirect) { s2_partial_insn_valid := false }
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when (io.cpu.req.valid) { s2_wrong_path := false }
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when (io.cpu.req.valid) { wrong_path := false }
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}
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io.cpu.resp <> fq.io.deq
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@ -27,6 +27,7 @@ case class DCacheParams(
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nMMIOs: Int = 1,
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blockBytes: Int = 64,
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acquireBeforeRelease: Boolean = false,
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pipelineWayMux: Boolean = false,
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scratch: Option[BigInt] = None) extends L1CacheParams {
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def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
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@ -528,7 +528,12 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val sboard = new Scoreboard(32, true)
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sboard.clear(ll_wen, ll_waddr)
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val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !(ll_wen && ll_waddr === rd))
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def id_sboard_clear_bypass(r: UInt) = {
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// ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check
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if (tileParams.dcache.get.dataECC.isInstanceOf[IdentityCode]) ll_wen && ll_waddr === r
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else div.io.resp.fire() && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r
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}
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val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd))
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sboard.set(wb_set_sboard && wb_wen, wb_waddr)
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// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
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