riscv/rocket-chip
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vlsi verilog compiles now but doesn't simulate

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This commit is contained in:
Andrew Waterman
2011-12-20 22:08:27 -08:00
parent 38ea10a5f4
commit d65e1a2eee
3 changed files with 102 additions and 134 deletions
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8
rocket/src/main/scala/util.scala
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@ -64,7 +64,6 @@ class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
val io = new ioArbiter(n)(data)
val vout = Wire { Bool() }
io.in(0).ready := io.out.ready
for (i <- 1 to n-1) {
@ -75,10 +74,9 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
for (i <- 1 to n-1)
dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
for (i <- 0 to n-2) {
when (io.in(i).valid) { vout <== Bool(true) }
}
vout <== io.in(n-1).valid
var vout = io.in(0).valid
for (i <- 1 to n-1)
vout = vout || io.in(i).valid
vout ^^ io.out.valid
dout ^^ io.out.bits