riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[commitlog] Added FP instructions to the commitlog

Browse Source
This commit is contained in:
Christopher Celio 2015-09-11 03:45:31 -07:00
parent 91458bef1c
commit d630a03857
2 changed files with 23 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
rocket/src/main/scala/fpu.scala
View File

@ -353,7 +353,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
io.out := Pipe(valid, res, latency-1)
}
class FPU extends Module
class FPU extends CoreModule
{
val io = new FPUIO
@ -383,7 +383,12 @@ class FPU extends Module
// regfile
val regfile = Mem(Bits(width = 65), 32)
when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
when (load_wb) {
regfile(load_wb_tag) := load_wb_data_recoded
if (EnableCommitLog) {
printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
}
}
val ex_ra1::ex_ra2::ex_ra3::Nil = List.fill(3)(Reg(UInt()))
when (io.valid) {
@ -459,7 +464,7 @@ class FPU extends Module
val winfo = Reg(Vec(Bits(), maxLatency-1))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
val mem_winfo = Cat(pipeid(mem_ctrl), mem_reg_inst(11,7))
val mem_winfo = Cat(mem_ctrl.single, pipeid(mem_ctrl), mem_reg_inst(11,7))
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { winfo(i) := winfo(i+1) }
@ -477,10 +482,18 @@ class FPU extends Module
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
val wsrc = winfo(0) >> 5
val wsrc = (winfo(0) >> 5)(1,0) // TODO: get rid of magic number on log(num_pipes)
val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.wdata))(wsrc))
val wexc = Vec(pipes.map(_.wexc))(wsrc)
when (wen(0) || divSqrt_wen) { regfile(waddr) := wdata }
when (wen(0) || divSqrt_wen) {
regfile(waddr) := wdata
if (EnableCommitLog) {
val wdata_unrec_s = hardfloat.recodedFloatNToFloatN(wdata(64,0), 23, 9)
val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12)
val wb_single = (winfo(0) >> 5)(2) // TODO: get rid of magic numbers
printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32), Mux(wb_single, wdata_unrec_s, wdata_unrec_d))
}
}
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)

10
rocket/src/main/scala/rocket.scala
View File

@ -43,6 +43,8 @@ abstract trait CoreParameters extends UsesParameters {
val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
val EnableCommitLog = true
if(params(FastLoadByte)) require(params(FastLoadWord))
}
@ -492,11 +494,9 @@ class Rocket extends CoreModule
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
val COMMITLOG = true
if (COMMITLOG) {
if (EnableCommitLog) {
val pc = Wire(SInt(width=64))
pc := wb_reg_pc//.toSInt()
pc := wb_reg_pc
val inst = wb_reg_inst
val rd = RegNext(RegNext(RegNext(id_waddr)))
val wfd = wb_ctrl.wfd
@ -506,7 +506,7 @@ class Rocket extends CoreModule
when (wb_valid) {
// TODO add privileged level
when (wfd) {
printf ("0x%x (0x%x) f%d\n", pc, inst, rd)
printf ("0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd+UInt(32))
}
.elsewhen (wxd && rd != UInt(0) && has_data) {
printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata)