riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

SystemBus: add stupidly many (4 more) buffers from sbus=>pbus

Browse Source 
This should probably be reverted.
This commit is contained in:
Wesley W. Terpstra
2017-08-30 13:57:08 -07:00
parent f7330028cc
commit d5b62dffda
1 changed files with 9 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/coreplex/SystemBus.scala
View File

@@ -36,7 +36,15 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlaves: TLOutwardNode = outwardSplitNode
val toPeripheryBus: TLOutwardNode = pbus_fixer.node
private val pbusBuffer0 = LazyModule(new TLBuffer(BufferParams.default))
private val pbusBuffer1 = LazyModule(new TLBuffer(BufferParams.default))
private val pbusBuffer2 = LazyModule(new TLBuffer(BufferParams.default))
private val pbusBuffer3 = LazyModule(new TLBuffer(BufferParams.default))
pbusBuffer0.node :*= pbus_fixer.node
pbusBuffer1.node :*= pbusBuffer0.node
pbusBuffer2.node :*= pbusBuffer1.node
pbusBuffer3.node :*= pbusBuffer2.node
val toPeripheryBus: TLOutwardNode = pbusBuffer3.node
val toMemoryBus: TLOutwardNode = outwardNode