From d5b62dffda92cd1e701062e4247c8ef877b0e15d Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 30 Aug 2017 13:57:08 -0700 Subject: [PATCH] SystemBus: add stupidly many (4 more) buffers from sbus=>pbus This should probably be reverted. --- src/main/scala/coreplex/SystemBus.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 05fc6081..bbbc45ff 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -36,7 +36,15 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr def toSplitSlaves: TLOutwardNode = outwardSplitNode - val toPeripheryBus: TLOutwardNode = pbus_fixer.node + private val pbusBuffer0 = LazyModule(new TLBuffer(BufferParams.default)) + private val pbusBuffer1 = LazyModule(new TLBuffer(BufferParams.default)) + private val pbusBuffer2 = LazyModule(new TLBuffer(BufferParams.default)) + private val pbusBuffer3 = LazyModule(new TLBuffer(BufferParams.default)) + pbusBuffer0.node :*= pbus_fixer.node + pbusBuffer1.node :*= pbusBuffer0.node + pbusBuffer2.node :*= pbusBuffer1.node + pbusBuffer3.node :*= pbusBuffer2.node + val toPeripheryBus: TLOutwardNode = pbusBuffer3.node val toMemoryBus: TLOutwardNode = outwardNode