riscv/rocket-chip
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fix I$ miss replay bug

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This commit is contained in:
Andrew Waterman 2012-01-21 20:42:13 -08:00
parent 31c56228e2
commit d59bddfbf1
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -592,7 +592,7 @@ class rocketCtrl extends Component
io.dpath.wen_btb := !ex_btb_match && br_jr_taken; io.dpath.wen_btb := !ex_btb_match && br_jr_taken;
io.dpath.clr_btb := ex_reg_btb_hit && !br_jr_taken || id_reg_icmiss; io.dpath.clr_btb := ex_reg_btb_hit && !br_jr_taken || id_reg_icmiss;
io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_icmiss) io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_replay)
// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage. // stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
val ex_mem_cmd_load = val ex_mem_cmd_load =