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coreplex: one IntNode per tile

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This commit is contained in:
Wesley W. Terpstra 2016-10-29 01:30:11 -07:00
parent e97844f71e
commit d52615c39e
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/coreplex/BaseCoreplex.scala
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@ -96,7 +96,7 @@ trait CoreplexRISCV {
// Build a set of Tiles // Build a set of Tiles
val lazyTiles = p(BuildTiles) map { _(p) } val lazyTiles = p(BuildTiles) map { _(p) }
val legacy = LazyModule(new TLLegacy()(outerMMIOParams)) val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
val tileIntNode = IntInternalOutputNode() // this should be moved into the Tile... val tileIntNodes = lazyTiles.map { _ => IntInternalOutputNode() } // this should be moved into the Tile...
val debug = LazyModule(new TLDebugModule()) val debug = LazyModule(new TLDebugModule())
val plic = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7)) val plic = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7))
@ -112,7 +112,7 @@ trait CoreplexRISCV {
clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.intnode := mmioInt plic.intnode := mmioInt
lazyTiles.foreach { _ => tileIntNode := plic.intnode } tileIntNodes.foreach { _ := plic.intnode }
} }
trait CoreplexRISCVBundle { trait CoreplexRISCVBundle {
@ -214,8 +214,8 @@ trait CoreplexRISCVModule {
tile.hartid := UInt(i) tile.hartid := UInt(i)
tile.resetVector := io.resetVector tile.resetVector := io.resetVector
tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i) tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
tile.interrupts.meip := outer.tileIntNode.bundleOut(i)(0) tile.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0)
tile.interrupts.seip.foreach(_ := outer.tileIntNode.bundleOut(i)(1)) tile.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1))
} }
outer.debug.module.io.db <> io.debug outer.debug.module.io.db <> io.debug