From d52615c39e6b08ddbe419becdbfebbcf1ac67121 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 29 Oct 2016 01:30:11 -0700 Subject: [PATCH] coreplex: one IntNode per tile --- src/main/scala/coreplex/BaseCoreplex.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 26e9b447..78f3f997 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -96,7 +96,7 @@ trait CoreplexRISCV { // Build a set of Tiles val lazyTiles = p(BuildTiles) map { _(p) } val legacy = LazyModule(new TLLegacy()(outerMMIOParams)) - val tileIntNode = IntInternalOutputNode() // this should be moved into the Tile... + val tileIntNodes = lazyTiles.map { _ => IntInternalOutputNode() } // this should be moved into the Tile... val debug = LazyModule(new TLDebugModule()) val plic = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7)) @@ -112,7 +112,7 @@ trait CoreplexRISCV { clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) plic.intnode := mmioInt - lazyTiles.foreach { _ => tileIntNode := plic.intnode } + tileIntNodes.foreach { _ := plic.intnode } } trait CoreplexRISCVBundle { @@ -214,8 +214,8 @@ trait CoreplexRISCVModule { tile.hartid := UInt(i) tile.resetVector := io.resetVector tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i) - tile.interrupts.meip := outer.tileIntNode.bundleOut(i)(0) - tile.interrupts.seip.foreach(_ := outer.tileIntNode.bundleOut(i)(1)) + tile.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0) + tile.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1)) } outer.debug.module.io.db <> io.debug