riscv/rocket-chip
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refined vector exception interface

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This commit is contained in:
Yunsup Lee
2012-03-03 16:11:54 -08:00
parent e28a551368
commit d4ec7ff4d9
5 changed files with 13 additions and 8 deletions
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8
rocket/src/main/scala/dpath_util.scala
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@ -80,7 +80,7 @@ class ioDpathPCR extends Bundle()
val vecbank = Bits(8, OUTPUT)
val vecbankcnt = UFix(4, OUTPUT)
val vec_eaddr = Bits(VADDR_BITS, OUTPUT)
val vec_exception = Bool(OUTPUT)
val vec_xcpt = Bits(3, OUTPUT)
}
class rocketDpathPCR extends Component
@ -100,7 +100,7 @@ class rocketDpathPCR extends Component
val reg_ptbr = Reg() { UFix() };
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_vec_eaddr = Reg() { Bits() }
val reg_vec_exception = Reg() { Bool() }
val reg_vec_xcpt = Reg() { Bits() }
val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false));
@ -143,7 +143,7 @@ class rocketDpathPCR extends Component
io.vecbankcnt := cnt(3,0)
io.vec_eaddr := reg_vec_eaddr
io.vec_exception := reg_vec_exception
io.vec_xcpt := reg_vec_xcpt
val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
when (io.badvaddr_wen) {
@ -212,7 +212,7 @@ class rocketDpathPCR extends Component
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
when (waddr === PCR_VEC_EADDR) { reg_vec_eaddr := wdata(VADDR_BITS,0) }
when (waddr === PCR_VEC_XCPT) { reg_vec_exception:= wdata(0) }
when (waddr === PCR_VEC_XCPT) { reg_vec_xcpt := wdata(2,0) }
}
rdata := Bits(0, 64)