diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 1568abb5..5ba224bf 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -144,7 +144,6 @@ object Constants
   val PCR_VECBANK  = UFix(18, 5);
 
   // temporaries for vector, these will go away
-  val PCR_VEC_CNT = UFix(29, 5)
   val PCR_VEC_EADDR = UFix(30, 5)
   val PCR_VEC_XCPT = UFix(31, 5)
 
diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index 90039b1f..ea2a2f26 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -200,6 +200,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
     // exceptions
     vu.io.cpu_exception.addr := dpath.io.vec_iface.eaddr.toUFix
     vu.io.cpu_exception.exception := dpath.io.vec_iface.exception
+    vu.io.cpu_exception.kill := dpath.io.vec_iface.kill
+    vu.io.cpu_exception.hold := dpath.io.vec_iface.hold
     ctrl.io.vec_iface.exception_ack_valid := vu.io.exception_ack_valid
     vu.io.exception_ack_ready := ctrl.io.vec_iface.exception_ack_ready
     ctrl.io.vec_iface.kill_ack_valid := vu.io.kill_ack_valid
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 817e001b..f14f80cb 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -384,7 +384,7 @@ class rocketDpath extends Component
     vec.io.wdata := wb_reg_vec_wdata
     vec.io.rs2 := wb_reg_rs2
     vec.io.vec_eaddr := pcr.io.vec_eaddr
-    vec.io.vec_exception := pcr.io.vec_exception
+    vec.io.vec_xcpt := pcr.io.vec_xcpt
 
     wb_wdata :=
       Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 6afc8a8e..7353c91f 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -80,7 +80,7 @@ class ioDpathPCR extends Bundle()
   val vecbank   = Bits(8, OUTPUT)
   val vecbankcnt = UFix(4, OUTPUT)
   val vec_eaddr  = Bits(VADDR_BITS, OUTPUT)
-  val vec_exception = Bool(OUTPUT)
+  val vec_xcpt = Bits(3, OUTPUT)
 }
 
 class rocketDpathPCR extends Component
@@ -100,7 +100,7 @@ class rocketDpathPCR extends Component
   val reg_ptbr     = Reg() { UFix() };
   val reg_vecbank  = Reg(resetVal = Bits("b1111_1111", 8))
   val reg_vec_eaddr = Reg() { Bits() }
-  val reg_vec_exception = Reg() { Bool() }
+  val reg_vec_xcpt = Reg() { Bits() }
   
   val reg_error_mode  = Reg(resetVal = Bool(false));
   val reg_status_vm   = Reg(resetVal = Bool(false));
@@ -143,7 +143,7 @@ class rocketDpathPCR extends Component
   io.vecbankcnt := cnt(3,0)
 
   io.vec_eaddr := reg_vec_eaddr
-  io.vec_exception := reg_vec_exception
+  io.vec_xcpt := reg_vec_xcpt
 
   val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
   when (io.badvaddr_wen) {
@@ -212,7 +212,7 @@ class rocketDpathPCR extends Component
     when (waddr === PCR_PTBR)     { reg_ptbr        := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
     when (waddr === PCR_VECBANK)  { reg_vecbank     := wdata(7,0) }
     when (waddr === PCR_VEC_EADDR) { reg_vec_eaddr    := wdata(VADDR_BITS,0) }
-    when (waddr === PCR_VEC_XCPT) { reg_vec_exception:= wdata(0) }
+    when (waddr === PCR_VEC_XCPT) { reg_vec_xcpt := wdata(2,0) }
   }
 
   rdata := Bits(0, 64)
diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala
index 012507af..86334e29 100644
--- a/rocket/src/main/scala/dpath_vec.scala
+++ b/rocket/src/main/scala/dpath_vec.scala
@@ -14,6 +14,8 @@ class ioDpathVecInterface extends Bundle
   val vcntq_bits = Bits(SZ_VLEN, OUTPUT)
   val eaddr = Bits(64, OUTPUT)
   val exception = Bool(OUTPUT)
+  val kill = Bool(OUTPUT)
+  val hold = Bool(OUTPUT)
 }
 
 class ioDpathVec extends Bundle
@@ -29,7 +31,7 @@ class ioDpathVec extends Bundle
   val wdata = Bits(64, INPUT)
   val rs2 = Bits(64, INPUT)
   val vec_eaddr = Bits(64, INPUT)
-  val vec_exception = Bool(INPUT)
+  val vec_xcpt = Bits(3, INPUT)
   val wen = Bool(OUTPUT)
   val appvl = UFix(12, OUTPUT)
 }
@@ -136,7 +138,9 @@ class rocketDpathVec extends Component
   io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0)
 
   io.iface.eaddr := io.vec_eaddr
-  io.iface.exception := io.vec_exception
+  io.iface.exception := io.vec_xcpt(0)
+  io.iface.kill := io.vec_xcpt(1)
+  io.iface.hold := io.vec_xcpt(2)
 
   io.ctrl.valid := io.valid
   io.ctrl.inst := io.inst