riscv/rocket-chip
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Reflect ISA changes

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Andrew Waterman committed 2013-08-24 14:43:55 -07:00
1 parent ff7b486006
commit d4a0db4575
12 files changed
+558 -597
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rocket/src/main/scala/tile.scala
-1
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@@ -15,7 +15,6 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
val xprlen = 64
val nxpr = 32
val nxprbits = log2Up(nxpr)
val rvc = false
if (fastLoadByte) require(fastLoadWord)
}