From d4a0db45752d4e9c1e14affb8b1117da893ae2b9 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 23 Aug 2013 21:16:28 -0700 Subject: [PATCH] Reflect ISA changes --- rocket/src/main/scala/ctrl.scala | 35 +- rocket/src/main/scala/ctrl_vec.scala | 5 +- rocket/src/main/scala/decode.scala | 31 +- rocket/src/main/scala/dpath.scala | 7 +- rocket/src/main/scala/dpath_util.scala | 91 ++- rocket/src/main/scala/fpu.scala | 12 +- rocket/src/main/scala/htif.scala | 7 +- rocket/src/main/scala/instructions.scala | 923 +++++++++++------------ rocket/src/main/scala/ptw.scala | 20 +- rocket/src/main/scala/tile.scala | 1 - rocket/src/main/scala/tlb.scala | 8 +- rocket/src/main/scala/util.scala | 15 +- 12 files changed, 558 insertions(+), 597 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 6831b144..46f4ad3b 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -93,9 +93,7 @@ object XDecode extends DecodeConstants J-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), JAL-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,WA_RA,WB_PC, PCR.N,N,N,N,N,N), - JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), - JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), - JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), + JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), @@ -146,9 +144,9 @@ object XDecode extends DecodeConstants SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - riscvAND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - riscvOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - riscvXOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + OR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + XOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), @@ -226,8 +224,8 @@ object FDecode extends DecodeConstants FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), - MFTX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), - MFTX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), @@ -242,8 +240,8 @@ object FDecode extends DecodeConstants FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), - MXTF_S-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), - MXTF_D-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMV_S_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMV_D_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), @@ -252,8 +250,8 @@ object FDecode extends DecodeConstants FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), - MFFSR-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), - MTFSR-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FRSR-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSSR-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), @@ -269,13 +267,10 @@ object VDecode extends DecodeConstants // | vec_val | | renx1 mem_val | | wen pcr | | | privileged // val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| | | s_wa s_wb | | | | | replay_next // | | | | | | | | | | | | | | | | | | | | | | | | - VVCFGIVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), - VVCFG-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), + VSETCFGVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), VSETVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), VF-> List(Y, N,Y,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), VMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), - VMSV-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - VFMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), FENCE_V_L-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), FENCE_V_G-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), VLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), @@ -454,22 +449,20 @@ class Control(implicit conf: RocketConfiguration) extends Module } else (Bool(false), Bool(false)) val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts) - val id_interrupt = io.dpath.status.et && id_interrupt_unmasked + val id_interrupt = io.dpath.status.ei && id_interrupt_unmasked def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) - // executing ERET when traps are enabled causes an illegal instruction exception - val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status.et) // flush pipeline on PCR writes that may have side effects val id_pcr_flush = id_pcr != PCR.N && id_pcr != PCR.F && - id_raddr1 != PCR.K0 && id_raddr1 != PCR.K1 && id_raddr1 != PCR.EPC + id_raddr1 != PCR.SUP0 && id_raddr1 != PCR.SUP1 && id_raddr1 != PCR.EPC val (id_xcpt, id_cause) = checkExceptions(List( (id_interrupt, id_interrupt_cause), (io.imem.resp.bits.xcpt_ma, UInt(0)), (io.imem.resp.bits.xcpt_if, UInt(1)), - (illegal_inst, UInt(2)), + (!id_int_val.toBool, UInt(2)), (id_privileged && !io.dpath.status.s, UInt(3)), (id_fp_val && !io.dpath.status.ef, UInt(4)), (id_syscall, UInt(6)), diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 2fa4c6f9..5e048742 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -109,13 +109,10 @@ class rocketCtrlVecDecoder extends Module // val vcmd vimm vimm2 | fn | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array( - VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,N), - VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,N), + VSETCFGVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,N), VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N), VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N), VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N), - VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N), - VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N), FENCE_V_L-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N), FENCE_V_G-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N), VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N), diff --git a/rocket/src/main/scala/decode.scala b/rocket/src/main/scala/decode.scala index 0a390da2..502c1fee 100644 --- a/rocket/src/main/scala/decode.scala +++ b/rocket/src/main/scala/decode.scala @@ -13,10 +13,10 @@ object DecodeLogic new Term(b.value) } } - def logic(addr: Bits, cache: scala.collection.mutable.Map[Term,Bits], terms: Seq[Term]) = { + def logic(addr: Bits, addrWidth: Int, cache: scala.collection.mutable.Map[Term,Bits], terms: Seq[Term]) = { terms.map { t => if (!cache.contains(t)) - cache += t -> ((if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addr.width)-(t.mask+1), addr.width){Bits()}) === Lit(t.value, addr.width){Bits()}) + cache += t -> ((if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addrWidth)-(t.mask+1), addrWidth){Bits()}) === Lit(t.value, addrWidth){Bits()}) cache(t).toBool }.foldLeft(Bool(false))(_||_) } @@ -27,19 +27,26 @@ object DecodeLogic val dlit = d.litOf val dterm = term(dlit) val (keys, values) = map.unzip - val keysterms = keys.toList.map(k => term(k.litOf)) zip values.toList.map(v => term(v.head.litOf)) + val addrWidth = keys.map(_.getWidth).max + val terms = keys.toList.map(k => term(k.litOf)) + val termvalues = terms zip values.toList.map(v => term(v.head.litOf)) + + for (t <- terms.tails; if !t.isEmpty) + for (u <- t.tail) + assert(!t.head.intersects(u), "DecodeLogic: keys " + t + " and " + u + " overlap") val result = (0 until math.max(dlit.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) => + val mint = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1) + val maxt = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1) + val dc = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1) + if (((dterm.mask >> i) & 1) != 0) { - var mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1) - var maxt = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1) - logic(addr, cache, SimplifyDC(mint, maxt, addr.width)).toBits + logic(addr, addrWidth, cache, SimplifyDC(mint, maxt, addrWidth)).toBits } else { - val want = 1 - ((dterm.value.toInt >> i) & 1) - val mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == want }.map(_._1) - val dc = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1) - val bit = logic(addr, cache, Simplify(mint, dc, addr.width)).toBits - if (want == 1) bit else ~bit + val defbit = (dterm.value.toInt >> i) & 1 + val t = if (defbit == 0) mint else maxt + val bit = logic(addr, addrWidth, cache, Simplify(t, dc, addrWidth)).toBits + if (defbit == 0) bit else ~bit } }).reverse.reduceRight(Cat(_,_)) map = map map { case (x,y) => (x, y.tail) } @@ -71,7 +78,7 @@ class Term(val value: BigInt, val mask: BigInt = 0) new Term(value &~ bit, mask | bit) } - override def toString = value.toString + "-" + mask + (if (prime) "p" else "") + override def toString = value.toString(16) + "-" + mask.toString(16) + (if (prime) "p" else "") } object Simplify diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 4e32be4c..f62e3327 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -199,7 +199,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.ctrl.pcr_replay := pcr.io.replay io.ptw.ptbr := pcr.io.ptbr - io.ptw.invalidate := pcr.io.ptbr_wen + io.ptw.invalidate := pcr.io.fatc io.ptw.eret := io.ctrl.eret io.ptw.status := pcr.io.status @@ -216,6 +216,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module val ex_pc_plus4 = ex_reg_pc.toSInt + Mux(ex_reg_sel_alu2 === A2_LTYPE, ex_reg_inst(26,7).toSInt << 12, SInt(4)) val ex_branch_target = ex_reg_pc.toSInt + (ex_imm << 1) + val ex_jalr_target = (ex_effective_address >> 1 << 1).toSInt val tsc_reg = WideCounter(64) val irt_reg = WideCounter(64, io.ctrl.wb_valid) @@ -327,8 +328,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.imem.req.bits.currentpc := ex_reg_pc io.imem.req.bits.pc := Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4, - Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address.toSInt, ex_branch_target), - Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec), + Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_jalr_target, ex_branch_target), + Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec, wb_reg_pc))).toUInt // PC_WB printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] %s\n", diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 4aae4679..6e3d00a9 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -58,15 +58,15 @@ class Status extends Bundle { val ip = Bits(width = 8) val im = Bits(width = 8) val zero = Bits(width = 7) + val ev = Bool() val vm = Bool() val s64 = Bool() val u64 = Bool() - val s = Bool() - val ps = Bool() - val ec = Bool() - val ev = Bool() val ef = Bool() - val et = Bool() + val pei = Bool() + val ei = Bool() + val ps = Bool() + val s = Bool() } object PCR @@ -81,20 +81,22 @@ object PCR val S = Bits(7,3) // setpcr // regs - val STATUS = 0 - val EPC = 1 - val BADVADDR = 2 - val EVEC = 3 - val COUNT = 4 - val COMPARE = 5 - val CAUSE = 6 - val PTBR = 7 - val SEND_IPI = 8 - val CLR_IPI = 9 - val COREID = 10 - val IMPL = 11 - val K0 = 12 - val K1 = 13 + val SUP0 = 0 + val SUP1 = 1 + val EPC = 2 + val BADVADDR = 3 + val PTBR = 4 + val ASID = 5 + val COUNT = 6 + val COMPARE = 7 + val EVEC = 8 + val CAUSE = 9 + val STATUS = 10 + val HARTID = 11 + val IMPL = 12 + val FATC = 13 + val SEND_IPI = 14 + val CLR_IPI = 15 val VECBANK = 18 val VECCFG = 19 val STATS = 28 @@ -116,7 +118,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module val status = new Status().asOutput val ptbr = UInt(OUTPUT, PADDR_BITS) - val evec = UInt(OUTPUT, VADDR_BITS) + val evec = UInt(OUTPUT, VADDR_BITS+1) val exception = Bool(INPUT) val cause = UInt(INPUT, 6) val badvaddr_wen = Bool(INPUT) @@ -126,7 +128,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module val eret = Bool(INPUT) val ei = Bool(INPUT) val di = Bool(INPUT) - val ptbr_wen = Bool(OUTPUT) + val fatc = Bool(OUTPUT) val irq_timer = Bool(OUTPUT) val irq_ipi = Bool(OUTPUT) val replay = Bool(OUTPUT) @@ -139,21 +141,19 @@ class PCR(implicit conf: RocketConfiguration) extends Module } import PCR._ - val reg_epc = Reg(Bits(width = conf.xprlen)) - val reg_badvaddr = Reg(Bits(width = conf.xprlen)) - val reg_ebase = Reg(Bits(width = conf.xprlen)) + val reg_epc = Reg(Bits(width = VADDR_BITS+1)) + val reg_badvaddr = Reg(Bits(width = VADDR_BITS)) + val reg_evec = Reg(Bits(width = VADDR_BITS)) val reg_count = WideCounter(32) val reg_compare = Reg(Bits(width = 32)) val reg_cause = Reg(Bits(width = io.cause.getWidth)) val reg_tohost = Reg(init=Bits(0, conf.xprlen)) val reg_fromhost = Reg(init=Bits(0, conf.xprlen)) - val reg_coreid = Reg(Bits(width = 16)) - val reg_k0 = Reg(Bits(width = conf.xprlen)) - val reg_k1 = Reg(Bits(width = conf.xprlen)) + val reg_sup0 = Reg(Bits(width = conf.xprlen)) + val reg_sup1 = Reg(Bits(width = conf.xprlen)) val reg_ptbr = Reg(UInt(width = PADDR_BITS)) val reg_vecbank = Reg(init=SInt(-1,8).toBits) val reg_stats = Reg(init=Bool(false)) - val reg_error_mode = Reg(init=Bool(false)) val reg_status = Reg(new Status) // reset down below val r_irq_timer = Reg(init=Bool(false)) @@ -185,10 +185,9 @@ class PCR(implicit conf: RocketConfiguration) extends Module io.status := reg_status io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), Bool(false), Bool(false), Bool(false), Bool(false)) - io.ptbr_wen := wen && addr === PTBR - io.evec := Mux(io.exception, reg_ebase, reg_epc).toUInt + io.fatc := wen && addr === FATC + io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt io.ptbr := reg_ptbr - io.host.debug.error_mode := reg_error_mode io.vecbank := reg_vecbank var cnt = UInt(0,4) @@ -206,19 +205,17 @@ class PCR(implicit conf: RocketConfiguration) extends Module } when (io.exception) { - when (!reg_status.et) { - reg_error_mode := true - } reg_status.s := true reg_status.ps := reg_status.s - reg_status.et := false + reg_status.ei := false + reg_status.pei := reg_status.ei reg_epc := io.pc.toSInt reg_cause := io.cause } when (io.eret) { reg_status.s := reg_status.ps - reg_status.et := true + reg_status.ei := reg_status.pei } when (reg_count === reg_compare) { @@ -238,10 +235,10 @@ class PCR(implicit conf: RocketConfiguration) extends Module val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0) val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) io.rw.rdata := AVec[Bits]( - io.status.toBits, reg_epc, reg_badvaddr, reg_ebase, - reg_count, reg_compare, read_cause, read_ptbr, - reg_coreid/*x*/, read_impl/*x*/, reg_coreid, read_impl, - reg_k0, reg_k1, reg_k0/*x*/, reg_k1/*x*/, + reg_sup0, reg_sup1, reg_epc, reg_badvaddr, + reg_ptbr, Bits(0)/*asid*/, reg_count, reg_compare, + reg_evec, reg_cause, io.status.toBits, io.host.id, + read_impl, read_impl/*x*/, read_impl/*x*/, read_impl/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg, reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, @@ -255,21 +252,21 @@ class PCR(implicit conf: RocketConfiguration) extends Module wdata)) reg_status := new Status().fromBits(sr_wdata) + reg_status.s64 := true + reg_status.u64 := true reg_status.zero := 0 if (!conf.vec) reg_status.ev := false if (!conf.fpu) reg_status.ef := false - if (!conf.rvc) reg_status.ec := false } when (addr === EPC) { reg_epc := wdata(VADDR_BITS,0).toSInt } - when (addr === EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toSInt } + when (addr === EVEC) { reg_evec := wdata(VADDR_BITS-1,0).toSInt } when (addr === COUNT) { reg_count := wdata.toUInt } when (addr === COMPARE) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false); } - when (addr === COREID) { reg_coreid := wdata(15,0) } when (addr === FROMHOST) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } } when (addr === TOHOST) { when (reg_tohost === UInt(0)) { reg_tohost := wdata } } when (addr === CLR_IPI) { r_irq_ipi := wdata(0) } - when (addr === K0) { reg_k0 := wdata; } - when (addr === K1) { reg_k1 := wdata; } + when (addr === SUP0) { reg_sup0 := wdata; } + when (addr === SUP1) { reg_sup1 := wdata; } when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt; } when (addr === VECBANK) { reg_vecbank:= wdata(7,0) } when (addr === STATS) { reg_stats := wdata(0) } @@ -279,10 +276,10 @@ class PCR(implicit conf: RocketConfiguration) extends Module when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) } when(this.reset) { - reg_status.et := false + reg_status.ei := false + reg_status.pei := false reg_status.ef := false reg_status.ev := false - reg_status.ec := false reg_status.ps := false reg_status.s := true reg_status.u64 := true diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index c6803a67..7e564800 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -79,8 +79,8 @@ class FPUDecoder extends Module FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N), FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N,N), FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N,N), - MXTF_S -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y,N,N), - MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y,N,N), + FMV_S_X -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y,N,N), + FMV_D_X -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y,N,N), @@ -89,8 +89,8 @@ class FPUDecoder extends Module FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y,N,N), - MFTX_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y,N,N), - MFTX_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y,N,N), + FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y,N,N), + FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), @@ -107,8 +107,8 @@ class FPUDecoder extends Module FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y,N,N), - MTFSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,Y), - MFFSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,N), + FSSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,Y), + FRSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,N), FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index f327dddd..2452883b 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -5,11 +5,6 @@ import Node._ import uncore._ import Util._ -class DebugIO extends Bundle -{ - val error_mode = Bool(OUTPUT); -} - class HostIO(val w: Int) extends Bundle { val clk = Bool(OUTPUT) @@ -28,7 +23,7 @@ class PCRReq extends Bundle class HTIFIO(ntiles: Int) extends Bundle { val reset = Bool(INPUT) - val debug = new DebugIO + val id = UInt(INPUT, log2Up(ntiles)) val pcr_req = Decoupled(new PCRReq).flip val pcr_rep = Decoupled(Bits(width = 64)) val ipi_req = Decoupled(Bits(width = log2Up(ntiles))) diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 3a2b94d5..a5d15e2d 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -5,262 +5,248 @@ import Node._ object Instructions { - // automatically generated by parse-opcodes - def J = Bits("b?????????????????????????_1100111",32); - def JAL = Bits("b?????????????????????????_1101111",32); - def JALR_C = Bits("b?????_?????_????????????_000_1101011",32); - def JALR_R = Bits("b?????_?????_????????????_001_1101011",32); - def JALR_J = Bits("b?????_?????_????????????_010_1101011",32); - def RDNPC = Bits("b?????_00000_000000000000_100_1101011",32); - def BEQ = Bits("b?????_?????_?????_???????_000_1100011",32); - def BNE = Bits("b?????_?????_?????_???????_001_1100011",32); - def BLT = Bits("b?????_?????_?????_???????_100_1100011",32); - def BGE = Bits("b?????_?????_?????_???????_101_1100011",32); - def BLTU = Bits("b?????_?????_?????_???????_110_1100011",32); - def BGEU = Bits("b?????_?????_?????_???????_111_1100011",32); - def LUI = Bits("b?????_????????????????????_0110111",32); - def AUIPC = Bits("b?????_????????????????????_0010111",32); - def ADDI = Bits("b?????_?????_????????????_000_0010011",32); - def SLLI = Bits("b?????_?????_000000_??????_001_0010011",32); - def SLTI = Bits("b?????_?????_????????????_010_0010011",32); - def SLTIU = Bits("b?????_?????_????????????_011_0010011",32); - def XORI = Bits("b?????_?????_????????????_100_0010011",32); - def SRLI = Bits("b?????_?????_000000_??????_101_0010011",32); - def SRAI = Bits("b?????_?????_000001_??????_101_0010011",32); - def ORI = Bits("b?????_?????_????????????_110_0010011",32); - def ANDI = Bits("b?????_?????_????????????_111_0010011",32); - def ADD = Bits("b?????_?????_?????_0000000000_0110011",32); - def SUB = Bits("b?????_?????_?????_1000000000_0110011",32); - def SLL = Bits("b?????_?????_?????_0000000001_0110011",32); - def SLT = Bits("b?????_?????_?????_0000000010_0110011",32); - def SLTU = Bits("b?????_?????_?????_0000000011_0110011",32); - def riscvXOR = Bits("b?????_?????_?????_0000000100_0110011",32); - def SRL = Bits("b?????_?????_?????_0000000101_0110011",32); - def SRA = Bits("b?????_?????_?????_1000000101_0110011",32); - def riscvOR = Bits("b?????_?????_?????_0000000110_0110011",32); - def riscvAND = Bits("b?????_?????_?????_0000000111_0110011",32); - def MUL = Bits("b?????_?????_?????_0000001000_0110011",32); - def MULH = Bits("b?????_?????_?????_0000001001_0110011",32); - def MULHSU = Bits("b?????_?????_?????_0000001010_0110011",32); - def MULHU = Bits("b?????_?????_?????_0000001011_0110011",32); - def DIV = Bits("b?????_?????_?????_0000001100_0110011",32); - def DIVU = Bits("b?????_?????_?????_0000001101_0110011",32); - def REM = Bits("b?????_?????_?????_0000001110_0110011",32); - def REMU = Bits("b?????_?????_?????_0000001111_0110011",32); - def ADDIW = Bits("b?????_?????_????????????_000_0011011",32); - def SLLIW = Bits("b?????_?????_000000_0_?????_001_0011011",32); - def SRLIW = Bits("b?????_?????_000000_0_?????_101_0011011",32); - def SRAIW = Bits("b?????_?????_000001_0_?????_101_0011011",32); - def ADDW = Bits("b?????_?????_?????_0000000000_0111011",32); - def SUBW = Bits("b?????_?????_?????_1000000000_0111011",32); - def SLLW = Bits("b?????_?????_?????_0000000001_0111011",32); - def SRLW = Bits("b?????_?????_?????_0000000101_0111011",32); - def SRAW = Bits("b?????_?????_?????_1000000101_0111011",32); - def MULW = Bits("b?????_?????_?????_0000001000_0111011",32); - def DIVW = Bits("b?????_?????_?????_0000001100_0111011",32); - def DIVUW = Bits("b?????_?????_?????_0000001101_0111011",32); - def REMW = Bits("b?????_?????_?????_0000001110_0111011",32); - def REMUW = Bits("b?????_?????_?????_0000001111_0111011",32); - def LB = Bits("b?????_?????_????????????_000_0000011",32); - def LH = Bits("b?????_?????_????????????_001_0000011",32); - def LW = Bits("b?????_?????_????????????_010_0000011",32); - def LD = Bits("b?????_?????_????????????_011_0000011",32); - def LBU = Bits("b?????_?????_????????????_100_0000011",32); - def LHU = Bits("b?????_?????_????????????_101_0000011",32); - def LWU = Bits("b?????_?????_????????????_110_0000011",32); - def SB = Bits("b?????_?????_?????_???????_000_0100011",32); - def SH = Bits("b?????_?????_?????_???????_001_0100011",32); - def SW = Bits("b?????_?????_?????_???????_010_0100011",32); - def SD = Bits("b?????_?????_?????_???????_011_0100011",32); - def AMOADD_W = Bits("b?????_?????_?????_0000000010_0101011",32); - def AMOSWAP_W = Bits("b?????_?????_?????_0000001010_0101011",32); - def AMOAND_W = Bits("b?????_?????_?????_0000010010_0101011",32); - def AMOOR_W = Bits("b?????_?????_?????_0000011010_0101011",32); - def AMOMIN_W = Bits("b?????_?????_?????_0000100010_0101011",32); - def AMOMAX_W = Bits("b?????_?????_?????_0000101010_0101011",32); - def AMOMINU_W = Bits("b?????_?????_?????_0000110010_0101011",32); - def AMOMAXU_W = Bits("b?????_?????_?????_0000111010_0101011",32); - def AMOADD_D = Bits("b?????_?????_?????_0000000011_0101011",32); - def AMOSWAP_D = Bits("b?????_?????_?????_0000001011_0101011",32); - def AMOAND_D = Bits("b?????_?????_?????_0000010011_0101011",32); - def AMOOR_D = Bits("b?????_?????_?????_0000011011_0101011",32); - def AMOMIN_D = Bits("b?????_?????_?????_0000100011_0101011",32); - def AMOMAX_D = Bits("b?????_?????_?????_0000101011_0101011",32); - def AMOMINU_D = Bits("b?????_?????_?????_0000110011_0101011",32); - def AMOMAXU_D = Bits("b?????_?????_?????_0000111011_0101011",32); - def LR_W = Bits("b?????_?????_00000_1000000010_0101011",32); - def LR_D = Bits("b?????_?????_00000_1000000011_0101011",32); - def SC_W = Bits("b?????_?????_?????_1000001010_0101011",32); - def SC_D = Bits("b?????_?????_?????_1000001011_0101011",32); - def FENCE_I = Bits("b?????_?????_????????????_001_0101111",32); - def FENCE = Bits("b?????_?????_????????????_010_0101111",32); - def SYSCALL = Bits("b00000_00000_00000_0000000000_1110111",32); - def BREAK = Bits("b00000_00000_00000_0000000001_1110111",32); - def RDCYCLE = Bits("b?????_00000_00000_0000000100_1110111",32); - def RDTIME = Bits("b?????_00000_00000_0000001100_1110111",32); - def RDINSTRET = Bits("b?????_00000_00000_0000010100_1110111",32); - def CLEARPCR = Bits("b?????_?????_????????????_000_1111011",32); - def SETPCR = Bits("b?????_?????_????????????_001_1111011",32); - def MFPCR = Bits("b?????_?????_00000_0000000010_1111011",32); - def MTPCR = Bits("b?????_?????_?????_0000000011_1111011",32); - def ERET = Bits("b00000_00000_00000_0000000100_1111011",32); - def CFLUSH = Bits("b00000_00000_00000_0000000101_1111011",32); - // floating point instructions - def FMOVZ = Bits("b?????_?????_?????_0000010101_1110111",32); - def FMOVN = Bits("b?????_?????_?????_0000011101_1110111",32); - def FADD_S = Bits("b?????_?????_?????_00000_???_00_1010011",32); - def FSUB_S = Bits("b?????_?????_?????_00001_???_00_1010011",32); - def FMUL_S = Bits("b?????_?????_?????_00010_???_00_1010011",32); - def FDIV_S = Bits("b?????_?????_?????_00011_???_00_1010011",32); - def FSQRT_S = Bits("b?????_?????_00000_00100_???_00_1010011",32); - def FSGNJ_S = Bits("b?????_?????_?????_00101_000_00_1010011",32); - def FSGNJN_S = Bits("b?????_?????_?????_00110_000_00_1010011",32); - def FSGNJX_S = Bits("b?????_?????_?????_00111_000_00_1010011",32); - def FADD_D = Bits("b?????_?????_?????_00000_???_01_1010011",32); - def FSUB_D = Bits("b?????_?????_?????_00001_???_01_1010011",32); - def FMUL_D = Bits("b?????_?????_?????_00010_???_01_1010011",32); - def FDIV_D = Bits("b?????_?????_?????_00011_???_01_1010011",32); - def FSQRT_D = Bits("b?????_?????_00000_00100_???_01_1010011",32); - def FSGNJ_D = Bits("b?????_?????_?????_00101_000_01_1010011",32); - def FSGNJN_D = Bits("b?????_?????_?????_00110_000_01_1010011",32); - def FSGNJX_D = Bits("b?????_?????_?????_00111_000_01_1010011",32); - def FCVT_L_S = Bits("b?????_?????_00000_01000_???_00_1010011",32); - def FCVT_LU_S = Bits("b?????_?????_00000_01001_???_00_1010011",32); - def FCVT_W_S = Bits("b?????_?????_00000_01010_???_00_1010011",32); - def FCVT_WU_S = Bits("b?????_?????_00000_01011_???_00_1010011",32); - def FCVT_L_D = Bits("b?????_?????_00000_01000_???_01_1010011",32); - def FCVT_LU_D = Bits("b?????_?????_00000_01001_???_01_1010011",32); - def FCVT_W_D = Bits("b?????_?????_00000_01010_???_01_1010011",32); - def FCVT_WU_D = Bits("b?????_?????_00000_01011_???_01_1010011",32); - def FCVT_S_L = Bits("b?????_?????_00000_01100_???_00_1010011",32); - def FCVT_S_LU = Bits("b?????_?????_00000_01101_???_00_1010011",32); - def FCVT_S_W = Bits("b?????_?????_00000_01110_???_00_1010011",32); - def FCVT_S_WU = Bits("b?????_?????_00000_01111_???_00_1010011",32); - def FCVT_D_L = Bits("b?????_?????_00000_01100_???_01_1010011",32); - def FCVT_D_LU = Bits("b?????_?????_00000_01101_???_01_1010011",32); - def FCVT_D_W = Bits("b?????_?????_00000_01110_???_01_1010011",32); - def FCVT_D_WU = Bits("b?????_?????_00000_01111_???_01_1010011",32); - def FCVT_S_D = Bits("b?????_?????_00000_10001_???_00_1010011",32); - def FCVT_D_S = Bits("b?????_?????_00000_10000_???_01_1010011",32); - def FEQ_S = Bits("b?????_?????_?????_10101_000_00_1010011",32); - def FLT_S = Bits("b?????_?????_?????_10110_000_00_1010011",32); - def FLE_S = Bits("b?????_?????_?????_10111_000_00_1010011",32); - def FEQ_D = Bits("b?????_?????_?????_10101_000_01_1010011",32); - def FLT_D = Bits("b?????_?????_?????_10110_000_01_1010011",32); - def FLE_D = Bits("b?????_?????_?????_10111_000_01_1010011",32); - def FMIN_S = Bits("b?????_?????_?????_11000_000_00_1010011",32); - def FMAX_S = Bits("b?????_?????_?????_11001_000_00_1010011",32); - def FMIN_D = Bits("b?????_?????_?????_11000_000_01_1010011",32); - def FMAX_D = Bits("b?????_?????_?????_11001_000_01_1010011",32); - def MFTX_S = Bits("b?????_?????_00000_11100_000_00_1010011",32); - def MFTX_D = Bits("b?????_?????_00000_11100_000_01_1010011",32); - def MFFSR = Bits("b?????_00000_00000_11101_000_00_1010011",32); - def MXTF_S = Bits("b?????_?????_00000_11110_000_00_1010011",32); - def MXTF_D = Bits("b?????_?????_00000_11110_000_01_1010011",32); - def MTFSR = Bits("b?????_?????_00000_11111_000_00_1010011",32); - def FLW = Bits("b?????_?????_????????????_010_0000111",32); - def FLD = Bits("b?????_?????_????????????_011_0000111",32); - def FSW = Bits("b?????_?????_?????_???????_010_0100111",32); - def FSD = Bits("b?????_?????_?????_???????_011_0100111",32); - def FMADD_S = Bits("b?????_?????_?????_?????_???_00_1000011",32); - def FMSUB_S = Bits("b?????_?????_?????_?????_???_00_1000111",32); - def FNMSUB_S = Bits("b?????_?????_?????_?????_???_00_1001011",32); - def FNMADD_S = Bits("b?????_?????_?????_?????_???_00_1001111",32); - def FMADD_D = Bits("b?????_?????_?????_?????_???_01_1000011",32); - def FMSUB_D = Bits("b?????_?????_?????_?????_???_01_1000111",32); - def FNMSUB_D = Bits("b?????_?????_?????_?????_???_01_1001011",32); - def FNMADD_D = Bits("b?????_?????_?????_?????_???_01_1001111",32); - // vector instructions - def FENCE_V_L = Bits("b?????_?????_????????????_100_0101111",32); - def FENCE_V_G = Bits("b?????_?????_????????????_101_0101111",32); - def MOVZ = Bits("b?????_?????_?????_0000000101_1110111",32); - def MOVN = Bits("b?????_?????_?????_0000001101_1110111",32); - def STOP = Bits("b00000_00000_00000_0000000010_1110111",32); - def UTIDX = Bits("b?????_00000_00000_0000000011_1110111",32); - def VLD = Bits("b?????_?????_00000_0000000011_0001011",32); - def VLW = Bits("b?????_?????_00000_0000000010_0001011",32); - def VLWU = Bits("b?????_?????_00000_0000000110_0001011",32); - def VLH = Bits("b?????_?????_00000_0000000001_0001011",32); - def VLHU = Bits("b?????_?????_00000_0000000101_0001011",32); - def VLB = Bits("b?????_?????_00000_0000000000_0001011",32); - def VLBU = Bits("b?????_?????_00000_0000000100_0001011",32); - def VFLD = Bits("b?????_?????_00000_0000001011_0001011",32); - def VFLW = Bits("b?????_?????_00000_0000001010_0001011",32); - def VLSTD = Bits("b?????_?????_?????_0000100011_0001011",32); - def VLSTW = Bits("b?????_?????_?????_0000100010_0001011",32); - def VLSTWU = Bits("b?????_?????_?????_0000100110_0001011",32); - def VLSTH = Bits("b?????_?????_?????_0000100001_0001011",32); - def VLSTHU = Bits("b?????_?????_?????_0000100101_0001011",32); - def VLSTB = Bits("b?????_?????_?????_0000100000_0001011",32); - def VLSTBU = Bits("b?????_?????_?????_0000100100_0001011",32); - def VFLSTD = Bits("b?????_?????_?????_0000101011_0001011",32); - def VFLSTW = Bits("b?????_?????_?????_0000101010_0001011",32); - def VLSEGD = Bits("b?????_?????_?????_0001000011_0001011",32); - def VLSEGW = Bits("b?????_?????_?????_0001000010_0001011",32); - def VLSEGWU = Bits("b?????_?????_?????_0001000110_0001011",32); - def VLSEGH = Bits("b?????_?????_?????_0001000001_0001011",32); - def VLSEGHU = Bits("b?????_?????_?????_0001000101_0001011",32); - def VLSEGB = Bits("b?????_?????_?????_0001000000_0001011",32); - def VLSEGBU = Bits("b?????_?????_?????_0001000100_0001011",32); - def VFLSEGD = Bits("b?????_?????_?????_0001001011_0001011",32); - def VFLSEGW = Bits("b?????_?????_?????_0001001010_0001011",32); - def VLSEGSTD = Bits("b?????_?????_?????_?????_100_11_0001011",32); - def VLSEGSTW = Bits("b?????_?????_?????_?????_100_10_0001011",32); - def VLSEGSTWU = Bits("b?????_?????_?????_?????_101_10_0001011",32); - def VLSEGSTH = Bits("b?????_?????_?????_?????_100_01_0001011",32); - def VLSEGSTHU = Bits("b?????_?????_?????_?????_101_01_0001011",32); - def VLSEGSTB = Bits("b?????_?????_?????_?????_100_00_0001011",32); - def VLSEGSTBU = Bits("b?????_?????_?????_?????_101_00_0001011",32); - def VFLSEGSTD = Bits("b?????_?????_?????_?????_110_11_0001011",32); - def VFLSEGSTW = Bits("b?????_?????_?????_?????_110_10_0001011",32); - def VSD = Bits("b?????_?????_00000_0000000011_0001111",32); - def VSW = Bits("b?????_?????_00000_0000000010_0001111",32); - def VSH = Bits("b?????_?????_00000_0000000001_0001111",32); - def VSB = Bits("b?????_?????_00000_0000000000_0001111",32); - def VFSD = Bits("b?????_?????_00000_0000001011_0001111",32); - def VFSW = Bits("b?????_?????_00000_0000001010_0001111",32); - def VSSTD = Bits("b?????_?????_?????_0000100011_0001111",32); - def VSSTW = Bits("b?????_?????_?????_0000100010_0001111",32); - def VSSTH = Bits("b?????_?????_?????_0000100001_0001111",32); - def VSSTB = Bits("b?????_?????_?????_0000100000_0001111",32); - def VFSSTD = Bits("b?????_?????_?????_0000101011_0001111",32); - def VFSSTW = Bits("b?????_?????_?????_0000101010_0001111",32); - def VSSEGD = Bits("b?????_?????_?????_0001000011_0001111",32); - def VSSEGW = Bits("b?????_?????_?????_0001000010_0001111",32); - def VSSEGH = Bits("b?????_?????_?????_0001000001_0001111",32); - def VSSEGB = Bits("b?????_?????_?????_0001000000_0001111",32); - def VFSSEGD = Bits("b?????_?????_?????_0001001011_0001111",32); - def VFSSEGW = Bits("b?????_?????_?????_0001001010_0001111",32); - def VSSEGSTD = Bits("b?????_?????_?????_?????_100_11_0001111",32); - def VSSEGSTW = Bits("b?????_?????_?????_?????_100_10_0001111",32); - def VSSEGSTH = Bits("b?????_?????_?????_?????_100_01_0001111",32); - def VSSEGSTB = Bits("b?????_?????_?????_?????_100_00_0001111",32); - def VFSSEGSTD = Bits("b?????_?????_?????_?????_110_11_0001111",32); - def VFSSEGSTW = Bits("b?????_?????_?????_?????_110_10_0001111",32); - def VMVV = Bits("b?????_?????_00000_0000000000_1110011",32); - def VMSV = Bits("b?????_?????_00000_0000010000_1110011",32); - def VMST = Bits("b?????_?????_?????_0000100000_1110011",32); - def VMTS = Bits("b?????_?????_?????_0000110000_1110011",32); - def VFMVV = Bits("b?????_?????_00000_0000000010_1110011",32); - def VFMSV = Bits("b?????_?????_00000_0000010010_1110011",32); - def VFMST = Bits("b?????_?????_?????_0000100010_1110011",32); - def VFMTS = Bits("b?????_?????_?????_0000110010_1110011",32); - def VVCFGIVL = Bits("b?????_?????_????????????_001_1110011",32); - def VTCFGIVL = Bits("b?????_?????_????????????_011_1110011",32); - def VVCFG = Bits("b00000_?????_?????_0000001000_1110011",32); - def VTCFG = Bits("b00000_?????_?????_0000011000_1110011",32); - def VSETVL = Bits("b?????_?????_000000000000_101_1110011",32); - def VF = Bits("b00000_?????_????????????_111_1110011",32); - // vector supervisor instructions - def VENQCMD = Bits("b00000_?????_?????_0001010110_1111011",32) - def VENQIMM1 = Bits("b00000_?????_?????_0001011110_1111011",32) - def VENQIMM2 = Bits("b00000_?????_?????_0001100110_1111011",32) - def VENQCNT = Bits("b00000_?????_?????_0001101110_1111011",32) - def VXCPTKILL = Bits("b00000_00000_00000_0000010110_1111011",32) - def VXCPTEVAC = Bits("b00000_?????_00000_0001000110_1111011",32) - def VXCPTHOLD = Bits("b00000_00000_00000_0001001110_1111011",32) - - def NOP = Bits("b00000_00000_000000000000_000_0010011",32); + /* Automatically generated by parse-opcodes */ + def J = Bits("b?????????????????????????1101011") + def JAL = Bits("b?????????????????????????1101111") + def JALR = Bits("b??????????????????????0001100111") + def BEQ = Bits("b??????????????????????0001100011") + def BNE = Bits("b??????????????????????0011100011") + def BLT = Bits("b??????????????????????1001100011") + def BGE = Bits("b??????????????????????1011100011") + def BLTU = Bits("b??????????????????????1101100011") + def BGEU = Bits("b??????????????????????1111100011") + def LUI = Bits("b?????????????????????????0110111") + def AUIPC = Bits("b?????????????????????????0010111") + def ADDI = Bits("b??????????????????????0000010011") + def SLLI = Bits("b??????????000000??????0010010011") + def SLTI = Bits("b??????????????????????0100010011") + def SLTIU = Bits("b??????????????????????0110010011") + def XORI = Bits("b??????????????????????1000010011") + def SRLI = Bits("b??????????000000??????1010010011") + def SRAI = Bits("b??????????000001??????1010010011") + def ORI = Bits("b??????????????????????1100010011") + def ANDI = Bits("b??????????????????????1110010011") + def ADD = Bits("b???????????????00000000000110011") + def SUB = Bits("b???????????????10000000000110011") + def SLL = Bits("b???????????????00000000010110011") + def SLT = Bits("b???????????????00000000100110011") + def SLTU = Bits("b???????????????00000000110110011") + def XOR = Bits("b???????????????00000001000110011") + def SRL = Bits("b???????????????00000001010110011") + def SRA = Bits("b???????????????10000001010110011") + def OR = Bits("b???????????????00000001100110011") + def AND = Bits("b???????????????00000001110110011") + def MUL = Bits("b???????????????00000010000110011") + def MULH = Bits("b???????????????00000010010110011") + def MULHSU = Bits("b???????????????00000010100110011") + def MULHU = Bits("b???????????????00000010110110011") + def DIV = Bits("b???????????????00000011000110011") + def DIVU = Bits("b???????????????00000011010110011") + def REM = Bits("b???????????????00000011100110011") + def REMU = Bits("b???????????????00000011110110011") + def ADDIW = Bits("b??????????????????????0000011011") + def SLLIW = Bits("b??????????0000000?????0010011011") + def SRLIW = Bits("b??????????0000000?????1010011011") + def SRAIW = Bits("b??????????0000010?????1010011011") + def ADDW = Bits("b???????????????00000000000111011") + def SUBW = Bits("b???????????????10000000000111011") + def SLLW = Bits("b???????????????00000000010111011") + def SRLW = Bits("b???????????????00000001010111011") + def SRAW = Bits("b???????????????10000001010111011") + def MULW = Bits("b???????????????00000010000111011") + def DIVW = Bits("b???????????????00000011000111011") + def DIVUW = Bits("b???????????????00000011010111011") + def REMW = Bits("b???????????????00000011100111011") + def REMUW = Bits("b???????????????00000011110111011") + def LB = Bits("b??????????????????????0000000011") + def LH = Bits("b??????????????????????0010000011") + def LW = Bits("b??????????????????????0100000011") + def LD = Bits("b??????????????????????0110000011") + def LBU = Bits("b??????????????????????1000000011") + def LHU = Bits("b??????????????????????1010000011") + def LWU = Bits("b??????????????????????1100000011") + def SB = Bits("b??????????????????????0000100011") + def SH = Bits("b??????????????????????0010100011") + def SW = Bits("b??????????????????????0100100011") + def SD = Bits("b??????????????????????0110100011") + def AMOADD_W = Bits("b???????????????00000000100101011") + def AMOSWAP_W = Bits("b???????????????00000010100101011") + def AMOAND_W = Bits("b???????????????00000100100101011") + def AMOOR_W = Bits("b???????????????00000110100101011") + def AMOMIN_W = Bits("b???????????????00001000100101011") + def AMOMAX_W = Bits("b???????????????00001010100101011") + def AMOMINU_W = Bits("b???????????????00001100100101011") + def AMOMAXU_W = Bits("b???????????????00001110100101011") + def AMOADD_D = Bits("b???????????????00000000110101011") + def AMOSWAP_D = Bits("b???????????????00000010110101011") + def AMOAND_D = Bits("b???????????????00000100110101011") + def AMOOR_D = Bits("b???????????????00000110110101011") + def AMOMIN_D = Bits("b???????????????00001000110101011") + def AMOMAX_D = Bits("b???????????????00001010110101011") + def AMOMINU_D = Bits("b???????????????00001100110101011") + def AMOMAXU_D = Bits("b???????????????00001110110101011") + def LR_W = Bits("b??????????0000010000000100101011") + def LR_D = Bits("b??????????0000010000000110101011") + def SC_W = Bits("b???????????????10000010100101011") + def SC_D = Bits("b???????????????10000010110101011") + def FENCE_I = Bits("b??????????????????????0010101111") + def FENCE = Bits("b??????????????????????0100101111") + def FENCE_V_L = Bits("b??????????????????????1000101111") + def FENCE_V_G = Bits("b??????????????????????1010101111") + def SYSCALL = Bits("b00000000000000000000000001110111") + def BREAK = Bits("b00000000000000000000000011110111") + def RDCYCLE = Bits("b?????000000000000000001001110111") + def RDTIME = Bits("b?????000000000000000011001110111") + def RDINSTRET = Bits("b?????000000000000000101001110111") + def MTPCR = Bits("b???????????????00000000001110011") + def MFPCR = Bits("b??????????0000000000000011110011") + def SETPCR = Bits("b??????????????????????0101110011") + def CLEARPCR = Bits("b??????????????????????0111110011") + def ERET = Bits("b00000000000000000000001001110011") + def FADD_S = Bits("b???????????????00000???001010011") + def FSUB_S = Bits("b???????????????00001???001010011") + def FMUL_S = Bits("b???????????????00010???001010011") + def FDIV_S = Bits("b???????????????00011???001010011") + def FSQRT_S = Bits("b??????????0000000100???001010011") + def FSGNJ_S = Bits("b???????????????00101000001010011") + def FSGNJN_S = Bits("b???????????????00110000001010011") + def FSGNJX_S = Bits("b???????????????00111000001010011") + def FADD_D = Bits("b???????????????00000???011010011") + def FSUB_D = Bits("b???????????????00001???011010011") + def FMUL_D = Bits("b???????????????00010???011010011") + def FDIV_D = Bits("b???????????????00011???011010011") + def FSQRT_D = Bits("b??????????0000000100???011010011") + def FSGNJ_D = Bits("b???????????????00101000011010011") + def FSGNJN_D = Bits("b???????????????00110000011010011") + def FSGNJX_D = Bits("b???????????????00111000011010011") + def FCVT_L_S = Bits("b??????????0000001000???001010011") + def FCVT_LU_S = Bits("b??????????0000001001???001010011") + def FCVT_W_S = Bits("b??????????0000001010???001010011") + def FCVT_WU_S = Bits("b??????????0000001011???001010011") + def FCVT_L_D = Bits("b??????????0000001000???011010011") + def FCVT_LU_D = Bits("b??????????0000001001???011010011") + def FCVT_W_D = Bits("b??????????0000001010???011010011") + def FCVT_WU_D = Bits("b??????????0000001011???011010011") + def FCVT_S_L = Bits("b??????????0000001100???001010011") + def FCVT_S_LU = Bits("b??????????0000001101???001010011") + def FCVT_S_W = Bits("b??????????0000001110???001010011") + def FCVT_S_WU = Bits("b??????????0000001111???001010011") + def FCVT_D_L = Bits("b??????????0000001100???011010011") + def FCVT_D_LU = Bits("b??????????0000001101???011010011") + def FCVT_D_W = Bits("b??????????0000001110???011010011") + def FCVT_D_WU = Bits("b??????????0000001111???011010011") + def FCVT_S_D = Bits("b??????????0000010001???001010011") + def FCVT_D_S = Bits("b??????????0000010000???011010011") + def FEQ_S = Bits("b???????????????10101000001010011") + def FLT_S = Bits("b???????????????10110000001010011") + def FLE_S = Bits("b???????????????10111000001010011") + def FEQ_D = Bits("b???????????????10101000011010011") + def FLT_D = Bits("b???????????????10110000011010011") + def FLE_D = Bits("b???????????????10111000011010011") + def FMIN_S = Bits("b???????????????11000000001010011") + def FMAX_S = Bits("b???????????????11001000001010011") + def FMIN_D = Bits("b???????????????11000000011010011") + def FMAX_D = Bits("b???????????????11001000011010011") + def FMV_X_S = Bits("b??????????0000011100000001010011") + def FMV_X_D = Bits("b??????????0000011100000011010011") + def FRSR = Bits("b?????000000000011101000001010011") + def FMV_S_X = Bits("b??????????0000011110000001010011") + def FMV_D_X = Bits("b??????????0000011110000011010011") + def FSSR = Bits("b??????????0000011111000001010011") + def FLW = Bits("b??????????????????????0100000111") + def FLD = Bits("b??????????????????????0110000111") + def FSW = Bits("b??????????????????????0100100111") + def FSD = Bits("b??????????????????????0110100111") + def FMADD_S = Bits("b???????????????????????001000011") + def FMSUB_S = Bits("b???????????????????????001000111") + def FNMSUB_S = Bits("b???????????????????????001001011") + def FNMADD_S = Bits("b???????????????????????001001111") + def FMADD_D = Bits("b???????????????????????011000011") + def FMSUB_D = Bits("b???????????????????????011000111") + def FNMSUB_D = Bits("b???????????????????????011001011") + def FNMADD_D = Bits("b???????????????????????011001111") + /* Automatically generated by parse-opcodes */ + def STOP = Bits("b00000000000000000000001011110111") + def UTIDX = Bits("b?????000000000000000001101110111") + def MOVZ = Bits("b???????????????00000001111110111") + def MOVN = Bits("b???????????????00000011111110111") + def FMOVZ = Bits("b???????????????00000101111110111") + def FMOVN = Bits("b???????????????00000111111110111") + def VSETCFGVL = Bits("b??????????????????????1110001011") + def VSETVL = Bits("b??????????0000000000001100001011") + def VMVV = Bits("b??????????0000000000011100001011") + def VGETCFG = Bits("b?????000000000000000001000001011") + def VGETVL = Bits("b?????000000000000000011000001011") + def VF = Bits("b??????????00000???????0100001011") + def VXCPTSAVE = Bits("b00000?????0000000000000110001011") + def VXCPTRESTORE = Bits("b00000?????0000000000010110001011") + def VXCPTKILL = Bits("b00000000000000000000100110001011") + def VXCPTEVAC = Bits("b00000?????0000000000110110001011") + def VXCPTHOLD = Bits("b00000000000000000001000110001011") + def VENQCMD = Bits("b00000??????????00001010110001011") + def VENQIMM1 = Bits("b00000??????????00001100110001011") + def VENQIMM2 = Bits("b00000??????????00001110110001011") + def VENQCNT = Bits("b00000??????????00010000110001011") + def VLD = Bits("b??????????0000000000110100001111") + def VLW = Bits("b??????????0000000000100100001111") + def VLWU = Bits("b??????????0000000001100100001111") + def VLH = Bits("b??????????0000000000010100001111") + def VLHU = Bits("b??????????0000000001010100001111") + def VLB = Bits("b??????????0000000000000100001111") + def VLBU = Bits("b??????????0000000001000100001111") + def VFLD = Bits("b??????????0000000010110100001111") + def VFLW = Bits("b??????????0000000010100100001111") + def VLSTD = Bits("b???????????????00000110110001111") + def VLSTW = Bits("b???????????????00000100110001111") + def VLSTWU = Bits("b???????????????00001100110001111") + def VLSTH = Bits("b???????????????00000010110001111") + def VLSTHU = Bits("b???????????????00001010110001111") + def VLSTB = Bits("b???????????????00000000110001111") + def VLSTBU = Bits("b???????????????00001000110001111") + def VFLSTD = Bits("b???????????????00010110110001111") + def VFLSTW = Bits("b???????????????00010100110001111") + def VLSEGD = Bits("b??????????00000???00110101011011") + def VLSEGW = Bits("b??????????00000???00100101011011") + def VLSEGWU = Bits("b??????????00000???01100101011011") + def VLSEGH = Bits("b??????????00000???00010101011011") + def VLSEGHU = Bits("b??????????00000???01010101011011") + def VLSEGB = Bits("b??????????00000???00000101011011") + def VLSEGBU = Bits("b??????????00000???01000101011011") + def VFLSEGD = Bits("b??????????00000???10110101011011") + def VFLSEGW = Bits("b??????????00000???10100101011011") + def VLSEGSTD = Bits("b??????????????????00110111011011") + def VLSEGSTW = Bits("b??????????????????00100111011011") + def VLSEGSTWU = Bits("b??????????????????01100111011011") + def VLSEGSTH = Bits("b??????????????????00010111011011") + def VLSEGSTHU = Bits("b??????????????????01010111011011") + def VLSEGSTB = Bits("b??????????????????00000111011011") + def VLSEGSTBU = Bits("b??????????????????01000111011011") + def VFLSEGSTD = Bits("b??????????00000???10110111011011") + def VFLSEGSTW = Bits("b??????????00000???10100111011011") + def VSD = Bits("b??????????0000010000110100001111") + def VSW = Bits("b??????????0000010000100100001111") + def VSH = Bits("b??????????0000010000010100001111") + def VSB = Bits("b??????????0000010000000100001111") + def VFSD = Bits("b??????????0000010010110100001111") + def VFSW = Bits("b??????????0000010010100100001111") + def VSSTD = Bits("b???????????????10000110110001111") + def VSSTW = Bits("b???????????????10000100110001111") + def VSSTH = Bits("b???????????????10000010110001111") + def VSSTB = Bits("b???????????????10000000110001111") + def VFSSTD = Bits("b???????????????10010110110001111") + def VFSSTW = Bits("b???????????????10010100110001111") + def VSSEGD = Bits("b??????????00000???00110101111011") + def VSSEGW = Bits("b??????????00000???00100101111011") + def VSSEGH = Bits("b??????????00000???00010101111011") + def VSSEGB = Bits("b??????????00000???00000101111011") + def VFSSEGD = Bits("b??????????00000???10110101111011") + def VFSSEGW = Bits("b??????????00000???10100101111011") + def VSSEGSTD = Bits("b??????????????????00110111111011") + def VSSEGSTW = Bits("b??????????????????00100111111011") + def VSSEGSTH = Bits("b??????????????????00010111111011") + def VSSEGSTB = Bits("b??????????????????00000111111011") + def VFSSEGSTD = Bits("b??????????00000???10110111111011") + def VFSSEGSTW = Bits("b??????????00000???10100111111011") } object Disassemble @@ -277,16 +263,16 @@ object Disassemble Str("s10"), Str("s11"), Str(" sp"), Str(" tp"), Str(" v0"), Str(" v1"), Str(" a0"), Str(" a1"), Str(" a2"), Str(" a3"), Str(" a4"), Str(" a5"), - Str(" a6"), Str(" a7"), Str(" a8"), Str(" a9"), - Str("a10"), Str("a11"), Str("a12"), Str("a13")) + Str(" a6"), Str(" a7"), Str(" t0"), Str(" t1"), + Str(" t2"), Str(" t3"), Str(" t4"), Str(" t5")) val f = AVec(Str(" fs0"), Str(" fs1"), Str(" fs2"), Str(" fs3"), Str(" fs4"), Str(" fs5"), Str(" fs6"), Str(" fs7"), Str(" fs8"), Str(" fs9"), Str("fs10"), Str("fs11"), Str("fs12"), Str("fs13"), Str("fs14"), Str("fs15"), Str(" fv0"), Str(" fv1"), Str(" fa0"), Str(" fa1"), Str(" fa2"), Str(" fa3"), Str(" fa4"), Str(" fa5"), - Str(" fa6"), Str(" fa7"), Str(" fa8"), Str(" fa9"), - Str("fa10"), Str("fa11"), Str("fa12"), Str("fa13")) + Str(" fa6"), Str(" fa7"), Str(" ft0"), Str(" ft1"), + Str(" ft2"), Str(" ft3"), Str(" ft4"), Str(" ft5")) def hex(x: SInt, plus: Char = ' ') = Cat(Mux(x < SInt(0), Str("-0x"), Str(plus + "0x")), Str(x.abs, 16)) @@ -303,13 +289,14 @@ object Disassemble val bmmv = Cat(insn(31,27), insn(16,10)).toSInt val jmmv = insn(31,7).toSInt - val imm = hex(immv) - val bmm = hex(bmmv << UInt(1)) + val imm = hex(Mux(fmt === FMT_B, bmmv << UInt(1), + Mux(fmt === FMT_I || fmt === FMT_LD || fmt === FMT_FLD, immv, + Mux(fmt === FMT_ST || fmt === FMT_FST, bmmv, + SInt(0))))) val jmm = hex(jmmv << UInt(1)) val lmm = Cat(Str("0x"), Str(insn(26,7).toUInt, 16)) - val laddr = Cat(Str(immv), lparen, x(rs1), rparen) - val saddr = Cat(Str(bmmv), lparen, x(rs1), rparen) + val addr = Cat(comma, imm, lparen, x(rs1), rparen) val r0 = x(rd) val r1 = Cat(r0, comma, x(rs1)) @@ -322,13 +309,13 @@ object Disassemble val xf2 = Cat(xf1, comma, f(rs2)) val z = Str(' ') val i = Cat(r1, comma, imm) - val b = Cat(x(rs1), comma, x(rs2), comma, bmm) + val b = Cat(x(rs1), comma, x(rs2), comma, imm) val j = jmm val l = Cat(x(rd), comma, lmm) - val ld = Cat(x(rd), comma, laddr) - val st = Cat(x(rs2), comma, saddr) - val fld = Cat(f(rd), comma, laddr) - val fst = Cat(f(rs2), comma, saddr) + val ld = Cat(x(rd), addr) + val st = Cat(x(rs2), addr) + val fld = Cat(f(rd), addr) + val fst = Cat(f(rs2), addr) val amo = r2 val opts = Seq(r0, r1, r2, f1, f2, f3, fx, xf1, xf2, z, i, b, j, l, ld, st, @@ -338,6 +325,7 @@ object Disassemble AVec(padded)(fmt.toUInt) } + private def FMT_X = Bits("b?????", 5) private def FMT_R0 = Bits(0, 5) private def FMT_R1 = Bits(1, 5) private def FMT_R2 = Bits(2, 5) @@ -358,221 +346,216 @@ object Disassemble private def FMT_FST = Bits(17, 5) private def FMT_AMO = Bits(18, 5) - private def default = List(Str("unknown "), FMT_0) + private def default = List(Str("unknown "), FMT_0) import Instructions._ private def table = Array( - BNE-> List(Str("bne "), FMT_B), - BEQ-> List(Str("beq "), FMT_B), - BLT-> List(Str("blt "), FMT_B), - BLTU-> List(Str("bltu "), FMT_B), - BGE-> List(Str("bge "), FMT_B), - BGEU-> List(Str("bgeu "), FMT_B), + BNE-> List(Str("bne "), FMT_B), + BEQ-> List(Str("beq "), FMT_B), + BLT-> List(Str("blt "), FMT_B), + BLTU-> List(Str("bltu "), FMT_B), + BGE-> List(Str("bge "), FMT_B), + BGEU-> List(Str("bgeu "), FMT_B), - J-> List(Str("j "), FMT_J), - JAL-> List(Str("jal "), FMT_J), - JALR_C-> List(Str("jalr.c "), FMT_LD), - JALR_J-> List(Str("jalr.j "), FMT_LD), - JALR_R-> List(Str("jalr.r "), FMT_LD), - AUIPC-> List(Str("auipc "), FMT_L), + J-> List(Str("j "), FMT_J), + JAL-> List(Str("jal "), FMT_J), + JALR-> List(Str("jalr "), FMT_LD), + AUIPC-> List(Str("auipc "), FMT_L), - LB-> List(Str("lb "), FMT_LD), - LH-> List(Str("lh "), FMT_LD), - LW-> List(Str("lw "), FMT_LD), - LD-> List(Str("ld "), FMT_LD), - LBU-> List(Str("lbu "), FMT_LD), - LHU-> List(Str("lhu "), FMT_LD), - LWU-> List(Str("lwu "), FMT_LD), - SB-> List(Str("sb "), FMT_ST), - SH-> List(Str("sh "), FMT_ST), - SW-> List(Str("sw "), FMT_ST), - SD-> List(Str("sd "), FMT_ST), + LB-> List(Str("lb "), FMT_LD), + LH-> List(Str("lh "), FMT_LD), + LW-> List(Str("lw "), FMT_LD), + LD-> List(Str("ld "), FMT_LD), + LBU-> List(Str("lbu "), FMT_LD), + LHU-> List(Str("lhu "), FMT_LD), + LWU-> List(Str("lwu "), FMT_LD), + SB-> List(Str("sb "), FMT_ST), + SH-> List(Str("sh "), FMT_ST), + SW-> List(Str("sw "), FMT_ST), + SD-> List(Str("sd "), FMT_ST), - AMOADD_W-> List(Str("amoadd.w "), FMT_AMO), - AMOSWAP_W-> List(Str("amoswap.w "), FMT_AMO), - AMOAND_W-> List(Str("amoand.w "), FMT_AMO), - AMOOR_W-> List(Str("amoor.w "), FMT_AMO), - AMOMIN_W-> List(Str("amomin.w "), FMT_AMO), - AMOMINU_W-> List(Str("amominu.w "), FMT_AMO), - AMOMAX_W-> List(Str("amomax.w "), FMT_AMO), - AMOMAXU_W-> List(Str("amomaxu.w "), FMT_AMO), - AMOADD_D-> List(Str("amoadd.d "), FMT_AMO), - AMOSWAP_D-> List(Str("amoswap.d "), FMT_AMO), - AMOAND_D-> List(Str("amoand.d "), FMT_AMO), - AMOOR_D-> List(Str("amoor.d "), FMT_AMO), - AMOMIN_D-> List(Str("amomin.d "), FMT_AMO), - AMOMINU_D-> List(Str("amominu.d "), FMT_AMO), - AMOMAX_D-> List(Str("amomax.d "), FMT_AMO), - AMOMAXU_D-> List(Str("amomaxu.d "), FMT_AMO), + AMOADD_W-> List(Str("amoaddw "), FMT_AMO), + AMOSWAP_W-> List(Str("amoswapw"), FMT_AMO), + AMOAND_W-> List(Str("amoandw "), FMT_AMO), + AMOOR_W-> List(Str("amoorw "), FMT_AMO), + AMOMIN_W-> List(Str("amominw "), FMT_AMO), + AMOMINU_W-> List(Str("amominuw"), FMT_AMO), + AMOMAX_W-> List(Str("amomaxw "), FMT_AMO), + AMOMAXU_W-> List(Str("amomaxuw"), FMT_AMO), + AMOADD_D-> List(Str("amoaddd "), FMT_AMO), + AMOSWAP_D-> List(Str("amoswapd"), FMT_AMO), + AMOAND_D-> List(Str("amoandd "), FMT_AMO), + AMOOR_D-> List(Str("amoord "), FMT_AMO), + AMOMIN_D-> List(Str("amomind "), FMT_AMO), + AMOMINU_D-> List(Str("amominud"), FMT_AMO), + AMOMAX_D-> List(Str("amomaxd "), FMT_AMO), + AMOMAXU_D-> List(Str("amomaxud"), FMT_AMO), - LR_W-> List(Str("lr.w "), FMT_AMO), - LR_D-> List(Str("lr.d "), FMT_AMO), - SC_W-> List(Str("sc.w "), FMT_AMO), - SC_D-> List(Str("sc.d "), FMT_AMO), + LR_W-> List(Str("lr.w "), FMT_AMO), + LR_D-> List(Str("lr.d "), FMT_AMO), + SC_W-> List(Str("sc.w "), FMT_AMO), + SC_D-> List(Str("sc.d "), FMT_AMO), - LUI-> List(Str("lui "), FMT_L), - ADDI-> List(Str("addi "), FMT_I), - SLTI -> List(Str("slti "), FMT_I), - SLTIU-> List(Str("sltiu "), FMT_I), - ANDI-> List(Str("andi "), FMT_I), - ORI-> List(Str("ori "), FMT_I), - XORI-> List(Str("xori "), FMT_I), - SLLI-> List(Str("slli "), FMT_I), - SRLI-> List(Str("srli "), FMT_I), - SRAI-> List(Str("srai "), FMT_I), - ADD-> List(Str("add "), FMT_R2), - SUB-> List(Str("sub "), FMT_R2), - SLT-> List(Str("slt "), FMT_R2), - SLTU-> List(Str("sltu "), FMT_R2), - riscvAND-> List(Str("and "), FMT_R2), - riscvOR-> List(Str("or "), FMT_R2), - riscvXOR-> List(Str("xor "), FMT_R2), - SLL-> List(Str("sll "), FMT_R2), - SRL-> List(Str("srl "), FMT_R2), - SRA-> List(Str("sra "), FMT_R2), + LUI-> List(Str("lui "), FMT_L), + ADDI-> List(Str("addi "), FMT_I), + SLTI -> List(Str("slti "), FMT_I), + SLTIU-> List(Str("sltiu "), FMT_I), + ANDI-> List(Str("andi "), FMT_I), + ORI-> List(Str("ori "), FMT_I), + XORI-> List(Str("xori "), FMT_I), + SLLI-> List(Str("slli "), FMT_I), + SRLI-> List(Str("srli "), FMT_I), + SRAI-> List(Str("srai "), FMT_I), + ADD-> List(Str("add "), FMT_R2), + SUB-> List(Str("sub "), FMT_R2), + SLT-> List(Str("slt "), FMT_R2), + SLTU-> List(Str("sltu "), FMT_R2), + AND-> List(Str("and "), FMT_R2), + OR-> List(Str("or "), FMT_R2), + XOR-> List(Str("xor "), FMT_R2), + SLL-> List(Str("sll "), FMT_R2), + SRL-> List(Str("srl "), FMT_R2), + SRA-> List(Str("sra "), FMT_R2), - ADDIW-> List(Str("addiw "), FMT_I), - SLLIW-> List(Str("slliw "), FMT_I), - SRLIW-> List(Str("srliw "), FMT_I), - SRAIW-> List(Str("sraiw "), FMT_I), - ADDW-> List(Str("addw "), FMT_R2), - SUBW-> List(Str("subw "), FMT_R2), - SLLW-> List(Str("sllw "), FMT_R2), - SRLW-> List(Str("srlw "), FMT_R2), - SRAW-> List(Str("sraw "), FMT_R2), + ADDIW-> List(Str("addiw "), FMT_I), + SLLIW-> List(Str("slliw "), FMT_I), + SRLIW-> List(Str("srliw "), FMT_I), + SRAIW-> List(Str("sraiw "), FMT_I), + ADDW-> List(Str("addw "), FMT_R2), + SUBW-> List(Str("subw "), FMT_R2), + SLLW-> List(Str("sllw "), FMT_R2), + SRLW-> List(Str("srlw "), FMT_R2), + SRAW-> List(Str("sraw "), FMT_R2), - MUL-> List(Str("mul "), FMT_R2), - MULH-> List(Str("mulh "), FMT_R2), - MULHU-> List(Str("mulhu "), FMT_R2), - MULHSU-> List(Str("mulhsu "), FMT_R2), - MULW-> List(Str("mulw "), FMT_R2), + MUL-> List(Str("mul "), FMT_R2), + MULH-> List(Str("mulh "), FMT_R2), + MULHU-> List(Str("mulhu "), FMT_R2), + MULHSU-> List(Str("mulhsu "), FMT_R2), + MULW-> List(Str("mulw "), FMT_R2), - DIV-> List(Str("div "), FMT_R2), - DIVU-> List(Str("divu "), FMT_R2), - REM-> List(Str("rem "), FMT_R2), - REMU-> List(Str("remu "), FMT_R2), - DIVW-> List(Str("divw "), FMT_R2), - DIVUW-> List(Str("divuw "), FMT_R2), - REMW-> List(Str("remw "), FMT_R2), - REMUW-> List(Str("remuw "), FMT_R2), + DIV-> List(Str("div "), FMT_R2), + DIVU-> List(Str("divu "), FMT_R2), + REM-> List(Str("rem "), FMT_R2), + REMU-> List(Str("remu "), FMT_R2), + DIVW-> List(Str("divw "), FMT_R2), + DIVUW-> List(Str("divuw "), FMT_R2), + REMW-> List(Str("remw "), FMT_R2), + REMUW-> List(Str("remuw "), FMT_R2), - SYSCALL-> List(Str("syscall "), FMT_0), - SETPCR-> List(Str("setpcr "), FMT_I), - CLEARPCR-> List(Str("clearpcr "), FMT_I), - ERET-> List(Str("eret "), FMT_0), - FENCE-> List(Str("fence "), FMT_0), - FENCE_I-> List(Str("fence.i "), FMT_0), - MFPCR-> List(Str("mfpcr "), FMT_R2), - MTPCR-> List(Str("mtpcr "), FMT_R2), - RDTIME-> List(Str("rdtime "), FMT_R0), - RDCYCLE-> List(Str("rdcycle "), FMT_R0), - RDINSTRET-> List(Str("rdinstret "), FMT_R0), + SYSCALL-> List(Str("syscall "), FMT_0), + SETPCR-> List(Str("setpcr "), FMT_I), + CLEARPCR-> List(Str("clearpcr"), FMT_I), + ERET-> List(Str("eret "), FMT_0), + FENCE-> List(Str("fence "), FMT_0), + FENCE_I-> List(Str("fence.i "), FMT_0), + MFPCR-> List(Str("mfpcr "), FMT_R2), + MTPCR-> List(Str("mtpcr "), FMT_R2), + RDTIME-> List(Str("rdtime "), FMT_R0), + RDCYCLE-> List(Str("rdcycle "), FMT_R0), + RDINSTRET-> List(Str("rdinstrt"), FMT_R0), - FCVT_S_D-> List(Str("fcvt.s.d "), FMT_F1), - FCVT_D_S-> List(Str("fcvt.d.s "), FMT_F1), - FSGNJ_S-> List(Str("fsgnj.s "), FMT_F2), - FSGNJ_D-> List(Str("fsgnj.d "), FMT_F2), - FSGNJX_S-> List(Str("fsgnx.s "), FMT_F2), - FSGNJX_D-> List(Str("fsgnx.d "), FMT_F2), - FSGNJN_S-> List(Str("fsgnjn.s "), FMT_F2), - FSGNJN_D-> List(Str("fsgnjn.d "), FMT_F2), - FMIN_S-> List(Str("fmin.s "), FMT_F2), - FMIN_D-> List(Str("fmin.d "), FMT_F2), - FMAX_S-> List(Str("fmax.s "), FMT_F2), - FMAX_D-> List(Str("fmax.d "), FMT_F2), - FADD_S-> List(Str("fadd.s "), FMT_F2), - FADD_D-> List(Str("fadd.d "), FMT_F2), - FSUB_S-> List(Str("fsub.s "), FMT_F2), - FSUB_D-> List(Str("fsub.d "), FMT_F2), - FMUL_S-> List(Str("fmul.s "), FMT_F2), - FMUL_D-> List(Str("fmul.d "), FMT_F2), - FMADD_S-> List(Str("fmadd.s "), FMT_F3), - FMADD_D-> List(Str("fmadd.d "), FMT_F3), - FMSUB_S-> List(Str("fmsub.s "), FMT_F3), - FMSUB_D-> List(Str("fmsub.d "), FMT_F3), - FNMADD_S-> List(Str("fnmadd.s "), FMT_F3), - FNMADD_D-> List(Str("fnmadd.d "), FMT_F3), - FNMSUB_S-> List(Str("fnmsub.s "), FMT_F3), - FNMSUB_D-> List(Str("fnmsub.d "), FMT_F3), - MFTX_S-> List(Str("mftx.s "), FMT_XF1), - MFTX_D-> List(Str("mftx.d "), FMT_XF1), - FCVT_W_S-> List(Str("fcvt.w.s "), FMT_XF1), - FCVT_W_D-> List(Str("fcvt.w.d "), FMT_XF1), - FCVT_WU_S-> List(Str("fcvt.wu.s "), FMT_XF1), - FCVT_WU_D-> List(Str("fcvt.wu.d "), FMT_XF1), - FCVT_L_S-> List(Str("fcvt.l.s "), FMT_XF1), - FCVT_L_D-> List(Str("fcvt.l.d "), FMT_XF1), - FCVT_LU_S-> List(Str("fcvt.lu.s "), FMT_XF1), - FCVT_LU_D-> List(Str("fcvt.lu.d "), FMT_XF1), - FEQ_S-> List(Str("feq.s "), FMT_XF2), - FEQ_D-> List(Str("feq.d "), FMT_XF2), - FLT_S-> List(Str("flt.s "), FMT_XF2), - FLT_D-> List(Str("flt.d "), FMT_XF2), - FLE_S-> List(Str("fle.s "), FMT_XF2), - FLE_D-> List(Str("fle.d "), FMT_XF2), - MXTF_S-> List(Str("mxtf.s "), FMT_FX), - MXTF_D-> List(Str("mxtf.d "), FMT_FX), - FCVT_S_W-> List(Str("fcvt.s.w "), FMT_FX), - FCVT_D_W-> List(Str("fcvt.d.w "), FMT_FX), - FCVT_S_WU-> List(Str("fcvt.s.wu "), FMT_FX), - FCVT_D_WU-> List(Str("fcvt.d.wu "), FMT_FX), - FCVT_S_L-> List(Str("fcvt.s.l "), FMT_FX), - FCVT_D_L-> List(Str("fcvt.d.l "), FMT_FX), - FCVT_S_LU-> List(Str("fcvt.s.lu "), FMT_FX), - FCVT_D_LU-> List(Str("fcvt.d.lu "), FMT_FX), - MFFSR-> List(Str("mffsr "), FMT_R0), - MTFSR-> List(Str("mtfsr "), FMT_R1), - FLW-> List(Str("flw "), FMT_FLD), - FLD-> List(Str("fld "), FMT_FLD), - FSW-> List(Str("fsw "), FMT_FST), - FSD-> List(Str("fsd "), FMT_FST), + FCVT_S_D-> List(Str("fcvt.sd "), FMT_F1), + FCVT_D_S-> List(Str("fcvt.ds "), FMT_F1), + FSGNJ_S-> List(Str("fsgnj.s "), FMT_F2), + FSGNJ_D-> List(Str("fsgnj.d "), FMT_F2), + FSGNJX_S-> List(Str("fsgnx.s "), FMT_F2), + FSGNJX_D-> List(Str("fsgnx.d "), FMT_F2), + FSGNJN_S-> List(Str("fsgnjn.s"), FMT_F2), + FSGNJN_D-> List(Str("fsgnjn.d"), FMT_F2), + FMIN_S-> List(Str("fmin.s "), FMT_F2), + FMIN_D-> List(Str("fmin.d "), FMT_F2), + FMAX_S-> List(Str("fmax.s "), FMT_F2), + FMAX_D-> List(Str("fmax.d "), FMT_F2), + FADD_S-> List(Str("fadd.s "), FMT_F2), + FADD_D-> List(Str("fadd.d "), FMT_F2), + FSUB_S-> List(Str("fsub.s "), FMT_F2), + FSUB_D-> List(Str("fsub.d "), FMT_F2), + FMUL_S-> List(Str("fmul.s "), FMT_F2), + FMUL_D-> List(Str("fmul.d "), FMT_F2), + FMADD_S-> List(Str("fmadd.s "), FMT_F3), + FMADD_D-> List(Str("fmadd.d "), FMT_F3), + FMSUB_S-> List(Str("fmsub.s "), FMT_F3), + FMSUB_D-> List(Str("fmsub.d "), FMT_F3), + FNMADD_S-> List(Str("fnmadd.s"), FMT_F3), + FNMADD_D-> List(Str("fnmadd.d"), FMT_F3), + FNMSUB_S-> List(Str("fnmsub.s"), FMT_F3), + FNMSUB_D-> List(Str("fnmsub.d"), FMT_F3), + FMV_X_S-> List(Str("fmv.x.s "), FMT_XF1), + FMV_X_D-> List(Str("fmv.x.d "), FMT_XF1), + FCVT_W_S-> List(Str("fcvt.ws "), FMT_XF1), + FCVT_W_D-> List(Str("fcvt.wd "), FMT_XF1), + FCVT_WU_S-> List(Str("fcvt.wus"), FMT_XF1), + FCVT_WU_D-> List(Str("fcvt.wud"), FMT_XF1), + FCVT_L_S-> List(Str("fcvt.ls "), FMT_XF1), + FCVT_L_D-> List(Str("fcvt.ld "), FMT_XF1), + FCVT_LU_S-> List(Str("fcvt.lus"), FMT_XF1), + FCVT_LU_D-> List(Str("fcvt.lud"), FMT_XF1), + FEQ_S-> List(Str("feq.s "), FMT_XF2), + FEQ_D-> List(Str("feq.d "), FMT_XF2), + FLT_S-> List(Str("flt.s "), FMT_XF2), + FLT_D-> List(Str("flt.d "), FMT_XF2), + FLE_S-> List(Str("fle.s "), FMT_XF2), + FLE_D-> List(Str("fle.d "), FMT_XF2), + FMV_S_X-> List(Str("fmv.s.x "), FMT_FX), + FMV_D_X-> List(Str("fmv.d.x "), FMT_FX), + FCVT_S_W-> List(Str("fcvt.sw "), FMT_FX), + FCVT_D_W-> List(Str("fcvt.dw "), FMT_FX), + FCVT_S_WU-> List(Str("fcvt.swu"), FMT_FX), + FCVT_D_WU-> List(Str("fcvt.dwu"), FMT_FX), + FCVT_S_L-> List(Str("fcvt.sl "), FMT_FX), + FCVT_D_L-> List(Str("fcvt.dl "), FMT_FX), + FCVT_S_LU-> List(Str("fcvt.slu"), FMT_FX), + FCVT_D_LU-> List(Str("fcvt.dlu"), FMT_FX), + FRSR-> List(Str("frsr "), FMT_R0), + FSSR-> List(Str("fssr "), FMT_R1), + FLW-> List(Str("flw "), FMT_FLD), + FLD-> List(Str("fld "), FMT_FLD), + FSW-> List(Str("fsw "), FMT_FST), + FSD-> List(Str("fsd "), FMT_FST), - VVCFGIVL-> List(Str("vecInst "), FMT_0), - VVCFG-> List(Str("vecInst "), FMT_0), - VSETVL-> List(Str("vecInst "), FMT_0), - VF-> List(Str("vecInst "), FMT_0), - VMVV-> List(Str("vecInst "), FMT_0), - VMSV-> List(Str("vecInst "), FMT_0), - VFMVV-> List(Str("vecInst "), FMT_0), - FENCE_V_L-> List(Str("vecInst "), FMT_0), - FENCE_V_G-> List(Str("vecInst "), FMT_0), - VLD-> List(Str("vecInst "), FMT_0), - VLW-> List(Str("vecInst "), FMT_0), - VLWU-> List(Str("vecInst "), FMT_0), - VLH-> List(Str("vecInst "), FMT_0), - VLHU-> List(Str("vecInst "), FMT_0), - VLB-> List(Str("vecInst "), FMT_0), - VLBU-> List(Str("vecInst "), FMT_0), - VSD-> List(Str("vecInst "), FMT_0), - VSW-> List(Str("vecInst "), FMT_0), - VSH-> List(Str("vecInst "), FMT_0), - VSB-> List(Str("vecInst "), FMT_0), - VFLD-> List(Str("vecInst "), FMT_0), - VFLW-> List(Str("vecInst "), FMT_0), - VFSD-> List(Str("vecInst "), FMT_0), - VFSW-> List(Str("vecInst "), FMT_0), - VLSTD-> List(Str("vecInst "), FMT_0), - VLSTW-> List(Str("vecInst "), FMT_0), - VLSTWU-> List(Str("vecInst "), FMT_0), - VLSTH-> List(Str("vecInst "), FMT_0), - VLSTHU-> List(Str("vecInst "), FMT_0), - VLSTB-> List(Str("vecInst "), FMT_0), - VLSTBU-> List(Str("vecInst "), FMT_0), - VSSTD-> List(Str("vecInst "), FMT_0), - VSSTW-> List(Str("vecInst "), FMT_0), - VSSTH-> List(Str("vecInst "), FMT_0), - VSSTB-> List(Str("vecInst "), FMT_0), - VFLSTD-> List(Str("vecInst "), FMT_0), - VFLSTW-> List(Str("vecInst "), FMT_0), - VFSSTD-> List(Str("vecInst "), FMT_0), - VFSSTW-> List(Str("vecInst "), FMT_0), + VSETCFGVL-> List(Str("vecInst "), FMT_0), + VSETVL-> List(Str("vecInst "), FMT_0), + VF-> List(Str("vecInst "), FMT_0), + VMVV-> List(Str("vecInst "), FMT_0), + FENCE_V_L-> List(Str("vecInst "), FMT_0), + FENCE_V_G-> List(Str("vecInst "), FMT_0), + VLD-> List(Str("vecInst "), FMT_0), + VLW-> List(Str("vecInst "), FMT_0), + VLWU-> List(Str("vecInst "), FMT_0), + VLH-> List(Str("vecInst "), FMT_0), + VLHU-> List(Str("vecInst "), FMT_0), + VLB-> List(Str("vecInst "), FMT_0), + VLBU-> List(Str("vecInst "), FMT_0), + VSD-> List(Str("vecInst "), FMT_0), + VSW-> List(Str("vecInst "), FMT_0), + VSH-> List(Str("vecInst "), FMT_0), + VSB-> List(Str("vecInst "), FMT_0), + VFLD-> List(Str("vecInst "), FMT_0), + VFLW-> List(Str("vecInst "), FMT_0), + VFSD-> List(Str("vecInst "), FMT_0), + VFSW-> List(Str("vecInst "), FMT_0), + VLSTD-> List(Str("vecInst "), FMT_0), + VLSTW-> List(Str("vecInst "), FMT_0), + VLSTWU-> List(Str("vecInst "), FMT_0), + VLSTH-> List(Str("vecInst "), FMT_0), + VLSTHU-> List(Str("vecInst "), FMT_0), + VLSTB-> List(Str("vecInst "), FMT_0), + VLSTBU-> List(Str("vecInst "), FMT_0), + VSSTD-> List(Str("vecInst "), FMT_0), + VSSTW-> List(Str("vecInst "), FMT_0), + VSSTH-> List(Str("vecInst "), FMT_0), + VSSTB-> List(Str("vecInst "), FMT_0), + VFLSTD-> List(Str("vecInst "), FMT_0), + VFLSTW-> List(Str("vecInst "), FMT_0), + VFSSTD-> List(Str("vecInst "), FMT_0), + VFSSTW-> List(Str("vecInst "), FMT_0), - VENQCMD-> List(Str("vecInst "), FMT_0), - VENQIMM1-> List(Str("vecInst "), FMT_0), - VENQIMM2-> List(Str("vecInst "), FMT_0), - VENQCNT-> List(Str("vecInst "), FMT_0), - VXCPTEVAC-> List(Str("vecInst "), FMT_0), - VXCPTKILL-> List(Str("vecInst "), FMT_0), - VXCPTHOLD-> List(Str("vecInst "), FMT_0) + VENQCMD-> List(Str("vecInst "), FMT_0), + VENQIMM1-> List(Str("vecInst "), FMT_0), + VENQIMM2-> List(Str("vecInst "), FMT_0), + VENQCNT-> List(Str("vecInst "), FMT_0), + VXCPTEVAC-> List(Str("vecInst "), FMT_0), + VXCPTKILL-> List(Str("vecInst "), FMT_0), + VXCPTHOLD-> List(Str("vecInst "), FMT_0) ) } diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 3681586c..f4acb1c5 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -72,9 +72,6 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module val resp_val = state === s_done || state === s_error val resp_err = state === s_error || state === s_wait - - val resp_ptd = io.mem.resp.bits.data(1,0) === Bits(1) - val resp_pte = io.mem.resp.bits.data(1,0) === Bits(2) val r_resp_ppn = io.mem.req.bits.addr >> PGIDX_BITS val resp_ppn = AVec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count) @@ -83,7 +80,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module val me = r_req_dest === UInt(i) io.requestor(i).resp.valid := resp_val && me io.requestor(i).resp.bits.error := resp_err - io.requestor(i).resp.bits.perm := r_pte(9,4) + io.requestor(i).resp.bits.perm := r_pte(8,3) io.requestor(i).resp.bits.ppn := resp_ppn.toUInt io.requestor(i).invalidate := io.dpath.invalidate io.requestor(i).eret := io.dpath.eret @@ -108,16 +105,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module state := s_req } when (io.mem.resp.valid) { - when (resp_pte) { // page table entry - state := s_done - } - .otherwise { - count := count + UInt(1) - when (resp_ptd && count < UInt(levels-1)) { + state := s_error + when (io.mem.resp.bits.data(0)) { + when (!io.mem.resp.bits.data(1)) { + state := s_done + }.elsewhen (count < levels-1) { state := s_req - } - .otherwise { - state := s_error + count := count + 1 } } } diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index c83be474..2bf49a68 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -15,7 +15,6 @@ case class RocketConfiguration(tl: TileLinkConfiguration, val xprlen = 64 val nxpr = 32 val nxprbits = log2Up(nxpr) - val rvc = false if (fastLoadByte) require(fastLoadWord) } diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 1c3af620..586e646c 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -121,12 +121,12 @@ class TLB(entries: Int) extends Module when (io.ptw.resp.valid) { tag_ram(r_refill_waddr) := io.ptw.resp.bits.ppn val perm = (!io.ptw.resp.bits.error).toSInt & io.ptw.resp.bits.perm(5,0) - ur_array := ur_array.bitSet(r_refill_waddr, perm(2)) + ur_array := ur_array.bitSet(r_refill_waddr, perm(0)) uw_array := uw_array.bitSet(r_refill_waddr, perm(1)) - ux_array := ux_array.bitSet(r_refill_waddr, perm(0)) - sr_array := sr_array.bitSet(r_refill_waddr, perm(5)) + ux_array := ux_array.bitSet(r_refill_waddr, perm(2)) + sr_array := sr_array.bitSet(r_refill_waddr, perm(3)) sw_array := sw_array.bitSet(r_refill_waddr, perm(4)) - sx_array := sx_array.bitSet(r_refill_waddr, perm(3)) + sx_array := sx_array.bitSet(r_refill_waddr, perm(5)) } // high if there are any unused (invalid) entries in the TLB diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index ed008423..9b735f1d 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -41,15 +41,14 @@ object Str def apply(x: UInt): Bits = apply(x, 10) def apply(x: UInt, radix: Int): Bits = { val rad = UInt(radix) - val digs = digits(radix) val w = x.getWidth require(w > 0) var q = x - var s = digs(q % rad) + var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad - s = Cat(Mux(Bool(radix == 10) && q === UInt(0), Str(' '), digs(q % rad)), s) + s = Cat(Mux(Bool(radix == 10) && q === UInt(0), Str(' '), digit(q % rad)), s) } s } @@ -61,28 +60,24 @@ object Str Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = UInt(radix) - val digs = digits(radix) val w = abs.getWidth require(w > 0) var q = abs - var s = digs(q % rad) + var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === UInt(0) val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace - s = Cat(Mux(placeSpace, space, digs(q % rad)), s) + s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } - private def digit(d: Int): Char = (if (d < 10) '0'+d else 'a'-10+d).toChar - private def digits(radix: Int): Vec[Bits] = - AVec((0 until radix).map(i => Str(digit(i)))) - + private def digit(d: UInt): Bits = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) }