riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Remove IPI network

Browse Source 
This is now provided via MMIO.
This commit is contained in:
Andrew Waterman
2015-11-16 21:52:24 -08:00
parent 0290635454
commit d426ecee78
1 changed files with 0 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
uncore/src/main/scala/htif.scala
View File

@@ -41,8 +41,6 @@ class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores)) val id = UInt(INPUT, log2Up(nCores))
val csr = new SMIIO(scrDataBits, 12).flip val csr = new SMIIO(scrDataBits, 12).flip
val ipi_req = Decoupled(Bits(width = log2Up(nCores)))
val ipi_rep = Decoupled(Bool()).flip
val debug_stats_csr = Bool(OUTPUT) val debug_stats_csr = Bool(OUTPUT)
// wired directly to stats register // wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
@@ -176,7 +174,6 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
val csrReadData = Reg(Bits(width = io.cpu(0).csr.resp.bits.getWidth)) val csrReadData = Reg(Bits(width = io.cpu(0).csr.resp.bits.getWidth))
for (i <- 0 until nCores) { for (i <- 0 until nCores) {
val my_reset = Reg(init=Bool(true)) val my_reset = Reg(init=Bool(true))
val my_ipi = Reg(init=Bool(false))
val cpu = io.cpu(i) val cpu = io.cpu(i)
val me = csr_coreid === UInt(i) val me = csr_coreid === UInt(i)
@@ -186,17 +183,6 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
cpu.csr.req.bits.data := csr_wdata cpu.csr.req.bits.data := csr_wdata
cpu.reset := my_reset cpu.reset := my_reset
when (cpu.ipi_rep.ready) {
my_ipi := Bool(false)
}
cpu.ipi_rep.valid := my_ipi
cpu.ipi_req.ready := Bool(true)
for (j <- 0 until nCores) {
when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UInt(i)) {
my_ipi := Bool(true)
}
}
when (cpu.csr.req.fire()) { state := state_csr_resp } when (cpu.csr.req.fire()) { state := state_csr_resp }
when (state === state_csr_req && me && csr_addr === UInt(csr_RESET)) { when (state === state_csr_req && me && csr_addr === UInt(csr_RESET)) {