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Massive update containing several months of changes from the now-defunct private chip repo.

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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
This commit is contained in:
Henry Cook
2015-06-25 23:17:35 -07:00
parent 12d8d8c5e3
commit d3ccec1044
19 changed files with 697 additions and 398 deletions
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24
vsim/vlsi_mem_gen
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@ -82,16 +82,6 @@ def gen_mem(name, width, depth, ports):
masked = len(maskedports)>0
tup = (depth, width, nr, nw, nrw, masked)
decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
decl.append('`ifndef SYNTHESIS')
decl.append(' integer initvar;')
decl.append(' initial begin')
decl.append(' #0.002;')
decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
decl.append(' end')
decl.append('`endif')
for pid in readports:
decl.append('reg [%d:0] reg_R%dA;' % (addr_width-1, pid))
sequential.append('if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid))
@ -115,6 +105,20 @@ def gen_mem(name, width, depth, ports):
combinational.append(' if (CLK && latch_W%dE)' % (pid))
combinational.append(' ram[latch_W%dA] <= latch_W%dI;' % (pid, pid))
decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
decl.append('`ifndef SYNTHESIS')
decl.append(' integer initvar;')
decl.append(' initial begin')
decl.append(' #0.002;')
decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
for pid in readports:
decl.append(' reg_R%dA = {%d {$random}};' % (pid, ((addr_width-1)/32+1)))
for pid in rwports:
decl.append(' reg_RW%dA = {%d {$random}};' % (pid, ((addr_width-1)/32+1)))
decl.append(' end')
decl.append('`endif')
decl.append("integer i;")
sequential.append("for (i = 0; i < %d; i=i+1) begin" % width)
for pid in writeports: