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Massive update containing several months of changes from the now-defunct private chip repo.

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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
This commit is contained in:
Henry Cook
2015-06-25 23:17:35 -07:00
parent 12d8d8c5e3
commit d3ccec1044
19 changed files with 697 additions and 398 deletions
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59
src/main/scala/Vlsi.scala
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@ -13,32 +13,43 @@ class MemDessert extends Module {
}
object VLSIUtils {
def doOuterMemorySystemSerdes(llc: MemPipeIO, mem: MemIO,
backup: MemSerializedIO, en: Bool, w: Int) {
val mem_serdes = Module(new MemSerdes(w))
val wide = mem_serdes.io.wide
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
mem.req_cmd.valid := llc.req_cmd.valid && !en
mem.req_cmd.bits := llc.req_cmd.bits
wide.req_cmd.valid := llc.req_cmd.valid && en
wide.req_cmd.bits := llc.req_cmd.bits
def doOuterMemorySystemSerdes(
llcs: Seq[MemIO],
mems: Seq[MemIO],
backup: MemSerializedIO,
en: Bool,
nMemChannels: Int) {
val arb = Module(new MemIOArbiter(nMemChannels))
val mem_serdes = Module(new MemSerdes)
mem_serdes.io.wide <> arb.io.outer
mem_serdes.io.narrow <> backup
llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
mem.req_data.valid := llc.req_data.valid && !en
mem.req_data.bits := llc.req_data.bits
wide.req_data.valid := llc.req_data.valid && en
wide.req_data.bits := llc.req_data.bits
llcs zip mems zip arb.io.inner foreach { case ((llc, mem), wide) =>
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
mem.req_cmd.valid := llc.req_cmd.valid && !en
mem.req_cmd.bits := llc.req_cmd.bits
wide.req_cmd.valid := llc.req_cmd.valid && en
wide.req_cmd.bits := llc.req_cmd.bits
llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
mem.resp.ready := Bool(true)
llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
mem.req_data.valid := llc.req_data.valid && !en
mem.req_data.bits := llc.req_data.bits
wide.req_data.valid := llc.req_data.valid && en
wide.req_data.bits := llc.req_data.bits
backup <> mem_serdes.io.narrow
llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
mem.resp.ready := llc.resp.ready && !en
wide.resp.ready := llc.resp.ready && en
}
}
def padOutHTIFWithDividedClock(htif: HTIFModuleIO, child: MemSerializedIO,
parent: MemSerializedIO, host: HostIO,
en: Bool, htifW: Int) {
def padOutHTIFWithDividedClock(
htif: HTIFModuleIO,
child: MemSerializedIO,
parent: MemBackupCtrlIO,
host: HostIO,
htifW: Int) {
val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
hio.io.set_divisor.bits := htif.scr.wdata
@ -50,10 +61,10 @@ object VLSIUtils {
child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
host.out.bits := hio.io.out_slow.bits
parent.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.req.ready)
parent.out_valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.out_ready)
val mem_backup_resp_valid = en && parent.resp.valid
val mem_backup_resp_valid = parent.en && parent.in_valid
hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid
hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits)
host.in.ready := hio.io.in_slow.ready