Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.
This commit is contained in:
Henry Cook
@ -7,157 +7,200 @@ import uncore._
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import rocket._
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import rocket.Util._
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case object NTiles extends Field[Int]
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case object NBanks extends Field[Int]
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case object NOutstandingMemReqs extends Field[Int]
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case object BankIdLSB extends Field[Int]
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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case object UseBackupMemoryPort extends Field[Boolean]
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case object Coherence extends Field[CoherencePolicyWithUncached]
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case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
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case object BuildTile extends Field[(Bool)=>Tile]
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/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
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abstract trait TopLevelParameters extends UsesParameters {
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/** Number of tiles */
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case object NTiles extends Field[Int]
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Whether to use the slow backup memory port [VLSI] */
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case object UseBackupMemoryPort extends Field[Boolean]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[() => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool) => Tile]]
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/** Which protocol to use to talk to memory/devices */
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case object UseNASTI extends Field[Boolean]
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/** Utility trait for quick access to some relevant parameters */
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trait TopLevelParameters extends UsesParameters {
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val htifW = params(HTIFWidth)
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val nTiles = params(NTiles)
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val nBanks = params(NBanks)
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val nMemChannels = params(NMemoryChannels)
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val nBanksPerMemChannel = params(NBanksPerMemoryChannel)
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val nBanks = nMemChannels*nBanksPerMemChannel
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val lsb = params(BankIdLSB)
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val refillCycles = params(MIFDataBeats)
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val nMemReqs = params(NOutstandingMemReqsPerChannel)
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val mifAddrBits = params(MIFAddrBits)
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val mifDataBeats = params(MIFDataBeats)
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require(lsb + log2Up(nBanks) < mifAddrBits)
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}
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class OuterMemorySystem extends Module with TopLevelParameters {
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val io = new Bundle {
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val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
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val htif = (new TileLinkIO).flip
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val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
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val mem = new MemIO
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val mem_backup = new MemSerializedIO(params(HTIFWidth))
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val mem_backup_en = Bool(INPUT)
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}
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// Create a simple NoC and points of coherence serialization
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val net = Module(new RocketChipCrossbarNetwork)
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster))
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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// Create a converter between TileLinkIO and MemIO
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val conv = Module(new MemPipeIOUncachedTileLinkIOConverter(
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params(NOutstandingMemReqs), refillCycles),
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{ case TLId => "outer" })
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if(params(NBanks) > 1) {
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)),
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{ case TLId => "outer" })
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arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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conv.io.uncached <> masterEndpoints.head.io.outer
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}
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// Create a SerDes for backup memory port
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if(params(UseBackupMemoryPort)) {
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VLSIUtils.doOuterMemorySystemSerdes(conv.io.mem, io.mem, io.mem_backup,
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io.mem_backup_en, htifW)
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} else {
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io.mem <> conv.io.mem
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}
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class MemBackupCtrlIO extends Bundle {
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val en = Bool(INPUT)
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val in_valid = Bool(INPUT)
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val out_ready = Bool(INPUT)
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val out_valid = Bool(OUTPUT)
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}
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/** Top-level io for the chip */
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class BasicTopIO extends Bundle {
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val host = new HostIO
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val mem_backup_ctrl = new MemBackupCtrlIO
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}
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class TopIO extends BasicTopIO {
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val mem = new MemIO
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}
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class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
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val mem = Vec.fill(nMemChannels){ new MemIO }
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}
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/** Top-level module for the chip */
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//TODO: Remove this wrapper once multichannel DRAM controller is provided
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class Top extends Module with TopLevelParameters {
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val io = new TopIO
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val temp = Module(new MultiChannelTop)
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val arb = Module(new MemIOArbiter(nMemChannels))
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arb.io.inner <> temp.io.mem
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io.mem <> arb.io.outer
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io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
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io.host <> temp.io.host
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}
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class MultiChannelTop extends Module with TopLevelParameters {
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val io = new MultiChannelTopIO
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// Build an Uncore and a set of Tiles
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val uncore = Module(new Uncore, {case TLId => "L1ToL2"})
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val tileList = uncore.io.htif zip params(BuildTiles) map { case(hl, bt) => bt(hl.reset) }
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// Connect each tile to the HTIF
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uncore.io.htif.zip(tileList).zipWithIndex.foreach {
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case ((hl, tile), i) =>
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached)
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached)
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uncore.io.host <> io.host
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uncore.io.mem <> io.mem
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if(params(UseBackupMemoryPort)) { uncore.io.mem_backup_ctrl <> io.mem_backup_ctrl }
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}
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/** Wrapper around everything that isn't a Tile.
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*
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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* Contains the Host-Target InterFace module (HTIF).
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*/
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class Uncore extends Module with TopLevelParameters {
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val io = new Bundle {
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val host = new HostIO
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val mem = new MemIO
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val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
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val mem = Vec.fill(nMemChannels){ new MemIO }
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val tiles_cached = Vec.fill(nTiles){new ClientTileLinkIO}.flip
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val tiles_uncached = Vec.fill(nTiles){new ClientUncachedTileLinkIO}.flip
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val htif = Vec.fill(nTiles){new HTIFIO}.flip
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val incoherent = Vec.fill(nTiles){Bool()}.asInput
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val mem_backup = new MemSerializedIO(htifW)
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val mem_backup_en = Bool(INPUT)
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val mem_backup_ctrl = new MemBackupCtrlIO
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}
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// Used to hash physical addresses to banks
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require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
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def addrToBank(addr: Bits): UInt = {
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if(nBanks > 1) addr( lsb + log2Up(nBanks) - 1, lsb)
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else UInt(0)
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}
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val htif = Module(new HTIF(CSRs.reset)) // One HTIF module per chip
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val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
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val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
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// Wire outer mem system to tiles and htif, adding
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// networking headers and endpoint queues
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(outmemsys.io.tiles :+ outmemsys.io.htif) // Collect outward-facing TileLink ports
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.zip(io.tiles :+ htif.io.mem) // Zip them with matching ports from clients
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.zipWithIndex // Index them
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.map { case ((outer, client), i) => // Then use the index and bank hash to
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// overwrite the networking header
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, nBanks, addrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, nBanks, addrToBank _))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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outmemsys.io.incoherent := (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
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outmemsys.io.htif_uncached <> htif.io.mem
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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// Wire the htif to the memory port(s) and host interface
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io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
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htif.io.cpu <> io.htif
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outmemsys.io.mem <> io.mem
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if(params(UseBackupMemoryPort)) {
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outmemsys.io.mem_backup_en := io.mem_backup_en
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VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup,
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io.mem_backup, io.host, io.mem_backup_en, htifW)
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outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
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VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
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} else {
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htif.io.host.out <> io.host.out
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htif.io.host.in <> io.host.in
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}
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}
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class TopIO extends Bundle {
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val host = new HostIO
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val mem = new MemIO
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val mem_backup_en = Bool(INPUT)
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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val out_mem_ready = Bool(INPUT)
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val out_mem_valid = Bool(OUTPUT)
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}
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class Top extends Module with TopLevelParameters {
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val io = new TopIO
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val resetSigs = Vec.fill(nTiles){Bool()}
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val tileList = (0 until nTiles).map(r => Module(params(BuildTile)(resetSigs(r))))
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val uncore = Module(new Uncore)
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for (i <- 0 until nTiles) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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val il = uncore.io.incoherent(i)
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resetSigs(i) := hl.reset
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val tile = tileList(i)
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tile.io.tilelink <> tl
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il := hl.reset
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
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/** The whole outer memory hierarchy, including a NoC, some kind of coherence
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* manager agent, and a converter from TileLink to MemIO.
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*/
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class OuterMemorySystem extends Module with TopLevelParameters {
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val io = new Bundle {
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val tiles_cached = Vec.fill(nTiles){new ClientTileLinkIO}.flip
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val tiles_uncached = Vec.fill(nTiles){new ClientUncachedTileLinkIO}.flip
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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val incoherent = Vec.fill(nTiles){Bool()}.asInput
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val mem = Vec.fill(nMemChannels){ new MemIO }
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val mem_backup = new MemSerializedIO(htifW)
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val mem_backup_en = Bool(INPUT)
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}
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io.host <> uncore.io.host
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io.mem <> uncore.io.mem
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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val ordered_clients = (io.tiles_cached ++ (io.tiles_uncached :+ io.htif_uncached).map(TileLinkIOWrapper(_)))
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: Bits): UInt = if(nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0)
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val preBuffering = TileLinkDepths(2,2,2,2,2)
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val postBuffering = TileLinkDepths(0,0,1,0,0) //TODO: had EOS24 crit path on inner.release
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val l1tol2net = Module(
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if(nBanks == 1) new RocketChipTileLinkArbiter(sharerToClientId, preBuffering, postBuffering)
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else new RocketChipTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering, postBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.fill(nMemChannels) {
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List.fill(nBanksPerMemChannel) {
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params(BuildL2CoherenceManager)()}}
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managerEndpoints.flatten.foreach { _.incoherent := io.incoherent }
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// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients <> ordered_clients
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l1tol2net.io.managers <> managerEndpoints.flatMap(_.map(_.innerTL))
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// Create a converter between TileLinkIO and MemIO for each channel
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val outerTLParams = params.alterPartial({ case TLId => "L2ToMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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val mem_channels = managerEndpoints.map { banks =>
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if(!params(UseNASTI)) {
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val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
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val conv = Module(new MemPipeIOTileLinkIOConverter(nMemReqs))(outerTLParams)
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arb.io.clients <> banks.map(_.outerTL)
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conv.io.tl <> arb.io.managers.head
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MemIOMemPipeIOConverter(conv.io.mem)
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} else {
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val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
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val conv1 = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams)
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val conv2 = Module(new MemIONASTISlaveIOConverter)
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val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs))
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arb.io.clients <> banks.map(_.outerTL)
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conv1.io.tl <> arb.io.managers.head
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conv2.io.nasti <> conv1.io.nasti
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conv3.io.cpu.req_cmd <> Queue(conv2.io.mem.req_cmd, 2)
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conv3.io.cpu.req_data <> Queue(conv2.io.mem.req_data, mifDataBeats)
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conv2.io.mem.resp <> conv3.io.cpu.resp
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MemIOMemPipeIOConverter(conv3.io.mem)
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}
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}
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// Create a SerDes for backup memory port
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if(params(UseBackupMemoryPort)) {
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uncore.io.mem_backup.resp.valid := io.in_mem_valid
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io.out_mem_valid := uncore.io.mem_backup.req.valid
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uncore.io.mem_backup.req.ready := io.out_mem_ready
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io.mem_backup_en <> uncore.io.mem_backup_en
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}
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VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels)
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} else { io.mem <> mem_channels }
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}
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Block a user