Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.
This commit is contained in:
Henry Cook
@ -4,88 +4,133 @@ package rocketchip
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import Chisel._
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import uncore._
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import scala.reflect._
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import scala.reflect.runtime.universe._
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object TileLinkHeaderOverwriter {
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def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = in.clone.asDirectionless
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out.bits.payload := in.bits.payload
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out.bits.header.src := UInt(clientId)
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out.bits.header.dst := (if(passThrough) in.bits.header.dst else UInt(0))
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out.valid := in.valid
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in.ready := out.ready
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out
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/** RocketChipNetworks combine a TileLink protocol with a particular physical
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* network implementation and chip layout.
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*
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* Specifically, they provide mappings between ClientTileLinkIO/
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* ManagerTileLinkIO channels and LogicalNetwork ports (i.e. generic
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* TileLinkIO with networking headers). Channels coming into the network have
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* appropriate networking headers appended and outgoing channels have their
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* headers stripped.
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*
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* @constructor base class constructor for Rocket NoC
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* @param addrToManagerId a mapping from a physical address to the network
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* id of a coherence manager
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* @param sharerToClientId a mapping from the id of a particular coherent
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* client (as determined by e.g. the directory) and the network id
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* of that client
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* @param clientDepths the depths of the queue that should be used to buffer
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* each channel on the client side of the network
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* @param managerDepths the depths of the queue that should be used to buffer
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* each channel on the manager side of the network
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*/
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abstract class RocketChipNetwork(
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addrToManagerId: UInt => UInt,
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sharerToClientId: UInt => UInt,
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clientDepths: TileLinkDepths,
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managerDepths: TileLinkDepths) extends TLModule {
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val nClients = params(TLNClients)
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val nManagers = params(TLNManagers)
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val io = new Bundle {
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val clients = Vec.fill(nClients){new ClientTileLinkIO}.flip
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val managers = Vec.fill(nManagers){new ManagerTileLinkIO}.flip
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}
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def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
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val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false)
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out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0))
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out
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val clients = io.clients.zipWithIndex.map {
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case (c, i) => {
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val p = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
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val q = Module(new TileLinkEnqueuer(clientDepths))
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p.io.client <> c
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q.io.client <> p.io.network
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q.io.manager
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}
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}
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val managers = io.managers.zipWithIndex.map {
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case (m, i) => {
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val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
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val q = Module(new TileLinkEnqueuer(managerDepths))
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m <> p.io.manager
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p.io.network <> q.io.manager
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q.io.client
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}
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}
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}
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class RocketChipCrossbarNetwork extends LogicalNetwork {
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val io = new Bundle {
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val clients = Vec.fill(params(LNClients)){(new TileLinkIO).flip}
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val masters = Vec.fill(params(LNMasters)){new TileLinkIO}
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/** A simple arbiter for each channel that also deals with header-based routing.
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* Assumes a single manager agent. */
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class RocketChipTileLinkArbiter(
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sharerToClientId: UInt => UInt = (u: UInt) => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)
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with TileLinkArbiterLike
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with PassesId {
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val arbN = nClients
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require(nManagers == 1)
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if(arbN > 1) {
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hookupClientSource(clients.map(_.acquire), managers.head.acquire)
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hookupClientSource(clients.map(_.release), managers.head.release)
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hookupFinish(clients.map(_.finish), managers.head.finish)
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hookupManagerSourceWithHeader(clients.map(_.probe), managers.head.probe)
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hookupManagerSourceWithHeader(clients.map(_.grant), managers.head.grant)
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} else {
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managers.head <> clients.head
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}
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}
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/** Provides a separate physical crossbar for each channel. Assumes multiple manager
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* agents. Managers are assigned to higher physical network port ids than
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* clients, and translations between logical network id and physical crossbar
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* port id are done automatically.
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*/
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class RocketChipTileLinkCrossbar(
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addrToManagerId: UInt => UInt = u => UInt(0),
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sharerToClientId: UInt => UInt = u => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths) {
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val n = params(LNEndpoints)
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val count = params(TLDataBeats)
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// Actually instantiate the particular networks required for TileLink
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val acqNet = Module(new BasicCrossbar(n, new Acquire))
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val relNet = Module(new BasicCrossbar(n, new Release))
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val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
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val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))
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val prbNet = Module(new BasicCrossbar(n, new Probe))
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val gntNet = Module(new BasicCrossbar(n, new Grant))
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val gntNet = Module(new BasicCrossbar(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData())))
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val ackNet = Module(new BasicCrossbar(n, new Finish))
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// Aliases for the various network IO bundle types
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type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
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type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
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type ToCrossbar[T <: Data] = FLNIO[T] => FBCIO[T]
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type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type LNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
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type FromCrossbar[T <: Data] = PNIO[T] => LNIO[T]
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type ToCrossbar[T <: Data] = LNIO[T] => PNIO[T]
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// Shims for converting between logical network IOs and physical network IOs
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//TODO: Could be less verbose if you could override subbundles after a <>
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def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = Decoupled(new LogicalNetworkIO(in.bits.payload)).asDirectionless
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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def crossbarToManagerShim[T <: Data](in: PNIO[T]): LNIO[T] = {
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val out = DefaultFromPhysicalShim(in)
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out.bits.header.src := in.bits.header.src - UInt(nManagers)
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out
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}
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def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = DefaultFromCrossbarShim(in)
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out.bits.header.src := in.bits.header.src - UInt(params(LNMasters))
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def crossbarToClientShim[T <: Data](in: PNIO[T]): LNIO[T] = {
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val out = DefaultFromPhysicalShim(in)
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out.bits.header.dst := in.bits.header.dst - UInt(nManagers)
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out
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}
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def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = DefaultFromCrossbarShim(in)
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out.bits.header.dst := in.bits.header.dst - UInt(params(LNMasters))
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def managerToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
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val out = DefaultToPhysicalShim(n, in)
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out.bits.header.dst := in.bits.header.dst + UInt(nManagers)
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out
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}
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def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = Decoupled(new PhysicalNetworkIO(n,in.bits.payload)).asDirectionless
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = DefaultToCrossbarShim(in)
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out.bits.header.dst := in.bits.header.dst + UInt(params(LNMasters))
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out
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}
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def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = DefaultToCrossbarShim(in)
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out.bits.header.src := in.bits.header.src + UInt(params(LNMasters))
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def clientToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
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val out = DefaultToPhysicalShim(n, in)
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out.bits.header.src := in.bits.header.src + UInt(nManagers)
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out
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}
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// Make an individual connection between virtual and physical ports using
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// a particular shim. Also seal the unused FIFO control signal.
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def doFIFOInputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: ToCrossbar[T]) = {
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// a particular shim. Also pin the unused Decoupled control signal low.
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def doDecoupledInputHookup[T <: Data](phys_in: PNIO[T], phys_out: PNIO[T], log_io: LNIO[T], shim: ToCrossbar[T]) = {
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val s = shim(log_io)
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phys_in.valid := s.valid
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phys_in.bits := s.bits
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@ -93,7 +138,7 @@ class RocketChipCrossbarNetwork extends LogicalNetwork {
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phys_out.ready := Bool(false)
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}
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def doFIFOOutputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: FromCrossbar[T]) = {
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def doDecoupledOutputHookup[T <: Data](phys_in: PNIO[T], phys_out: PNIO[T], log_io: LNIO[T], shim: FromCrossbar[T]) = {
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val s = shim(phys_out)
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log_io.valid := s.valid
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log_io.bits := s.bits
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@ -101,29 +146,31 @@ class RocketChipCrossbarNetwork extends LogicalNetwork {
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phys_in.valid := Bool(false)
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}
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def doFIFOHookup[T <: Data](isEndpointSourceOfMessage: Boolean, physIn: FBCIO[T], physOut: FBCIO[T], logIO: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
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if(isEndpointSourceOfMessage) doFIFOInputHookup(physIn, physOut, logIO, inShim)
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else doFIFOOutputHookup(physIn, physOut, logIO, outShim)
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}
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//Hookup all instances of a particular subbundle of TileLink
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def doFIFOHookups[T <: Data: TypeTag](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => FLNIO[T]) = {
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typeTag[T].tpe match{
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case t if t <:< typeTag[ClientSourcedMessage].tpe => {
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io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
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io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
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def doDecoupledHookups[T <: Data](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => LNIO[T]) = {
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physIO.in.head.bits.payload match {
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case c: ClientToManagerChannel => {
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managers.zipWithIndex.map { case (i, id) =>
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doDecoupledOutputHookup(physIO.in(id), physIO.out(id), getLogIO(i), crossbarToManagerShim[T])
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}
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clients.zipWithIndex.map { case (i, id) =>
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doDecoupledInputHookup(physIO.in(id+nManagers), physIO.out(id+nManagers), getLogIO(i), clientToCrossbarShim[T])
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}
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}
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case t if t <:< typeTag[MasterSourcedMessage].tpe => {
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io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
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io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
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case m: ManagerToClientChannel => {
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managers.zipWithIndex.map { case (i, id) =>
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doDecoupledInputHookup(physIO.in(id), physIO.out(id), getLogIO(i), managerToCrossbarShim[T])
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}
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clients.zipWithIndex.map { case (i, id) =>
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doDecoupledOutputHookup(physIO.in(id+nManagers), physIO.out(id+nManagers), getLogIO(i), crossbarToClientShim[T])
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}
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}
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case _ => require(false, "Unknown message sourcing.")
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}
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}
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doFIFOHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
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doFIFOHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doFIFOHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doFIFOHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.finish)
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doDecoupledHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
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doDecoupledHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doDecoupledHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doDecoupledHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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doDecoupledHookups(ackNet.io, (tl: TileLinkIO) => tl.finish)
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}
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