Massive update containing several months of changes from the now-defunct private chip repo.

* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.

regression.sh

@@ -0,0 +1,31 @@
+#! /bin/bash
+#
+# See LICENSE for license details.
+
+# Script to setup submodules, build rocket-chip, and run asm tests, and optionally run torture
+
+echo "Starting Rocket-chip regression test"
+if [ $# -lt 1 ]
+then
+  echo "Usage: ./regression.sh config [torture_config] [torture_output_dir]"
+  exit
+fi
+
+git submodule update --init --recursive riscv-tools
+export RISCV="$(pwd)/install"; export PATH=$PATH:$RISCV/bin
+cd riscv-tools; ./build.sh; cd ..
+git submodule update --init 
+git submodule status --recursive
+cd emulator; make CONFIG=$1 run-asm-tests; cd ..
+if [ $# -ge 2 ]
+then
+  git clone git@github.com:ucb-bar/riscv-torture.git
+  cd riscv-torture; git submodule update --init;
+  if [ $# -eq 3 ]
+  then
+    make cnight RTL_CONFIG=$1 OPTIONS="-C $2 -p $3 -m 30 -t 10"
+  else
+    make cnight RTL_CONFIG=$1 OPTIONS="-C $2 -m 30 -t 10"
+  fi
+fi
+