build: remove the now obsolete config string

src/main/scala/coreplex/RISCVPlatform.scala

@@ -24,11 +24,6 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
 
   plic.intnode := intBar.intnode
 
-  lazy val configString = {
-    val managers = l1tol2.node.edgesIn(0).manager.managers
-    rocketchip.GenerateConfigString(p, clint, plic, managers)
-  }
-
   lazy val dts = DTS(bindingTree)
 }
 
@@ -52,9 +47,6 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
   val rtcLast = Reg(init = Bool(false), next=rtcSync)
   outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
 
-  println(s"\nGenerated Configuration String\n${outer.configString}")
-  ElaborationArtefacts.add("cfg", outer.configString)
-
   println(outer.dts)
   ElaborationArtefacts.add("dts", outer.dts)
 }

src/main/scala/rocketchip/Periphery.scala

@@ -305,7 +305,7 @@ trait PeripheryBootROM {
 
   private val bootrom_address = 0x1000
   private val bootrom_size = 0x1000
-  private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
+  private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dts)
   val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
   bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
 }

src/main/scala/rocketchip/Utils.scala

@@ -52,50 +52,18 @@ class GlobalVariable[T] {
   def get: T = { require(assigned); variable }
 }
 
-object GenerateConfigString {
-  def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
-    val c = CoreplexParameters()(p)
-    val res = new StringBuilder
-    res append plic.globalConfigString
-    res append clint.globalConfigString
-    res append  "core {\n"
-    c.tilesParams.zipWithIndex.map { case(t, i) => 
-      val isa = {
-        val m = if (t.core.mulDiv.nonEmpty) "m" else ""
-        val a = if (t.core.useAtomics) "a" else ""
-        val f = if (t.core.fpu.nonEmpty) "f" else ""
-        val d = if (t.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
-        val c = if (t.core.useCompressed) "c" else ""
-        val s = if (t.core.useVM) "s" else ""
-        s"rv${p(XLen)}i$m$a$f$d$c$s"
-      }
-      res append s"  $i {\n"
-      res append  "    0 {\n"
-      res append s"      isa $isa;\n"
-      res append clint.hartConfigStrings(i)
-      res append plic.hartConfigStrings(i)
-      res append  "    };\n"
-      res append  "  };\n"
-    }
-    res append  "};\n"
-    peripheryManagers.foreach { manager => res append manager.dts }
-    res append '\u0000'
-    res.toString
-  }
-}
-
 object GenerateBootROM {
-  def apply(p: Parameters, address: BigInt, configString: String) = {
+  def apply(p: Parameters, address: BigInt, dts: String) = {
     val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
     val rom = ByteBuffer.wrap(romdata)
 
     rom.order(ByteOrder.LITTLE_ENDIAN)
 
     require(address == address.toInt)
-    val configStringAddr = address.toInt + rom.capacity
+    val dtsAddr = address.toInt + rom.capacity
     require(rom.getInt(12) == 0,
-      "Config string address position should not be occupied by code")
+      "DTS address position should not be occupied by code")
-    rom.putInt(12, configStringAddr)
+    rom.putInt(12, dtsAddr)
-    rom.array() ++ (configString.getBytes.toSeq)
+    rom.array() ++ (dts.getBytes.toSeq)
   }
 }

src/main/scala/uncore/devices/Plic.scala

@@ -89,38 +89,6 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
   def nPriorities = min(maxPriorities, nDevices)
   def nHarts = intnode.edgesOut.map(_.source.num).sum
 
-  def context(i: Int, mode: Char) = mode match {
-    case 'M' => i * contextsPerHart
-    case 'S' => require(supervisor); i * contextsPerHart + 1
-  }
-  def claimAddr(i: Int, mode: Char)  = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
-  def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
-  def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
-
-  // Create the global PLIC config string
-  lazy val globalConfigString = Seq(
-    s"plic {\n",
-    s"  priority 0x${address.toString(16)};\n",
-    s"  pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
-    s"  ndevs ${nDevices};\n",
-    s"};\n").mkString
-
-  // Create the per-Hart config string
-  lazy val hartConfigStrings = Seq.tabulate(intnode.edgesOut.size) { i => (Seq(
-    s"      plic {\n",
-    s"        m {\n",
-    s"         ie 0x${enableAddr(i, 'M').toString(16)};\n",
-    s"         thresh 0x${threshAddr(i, 'M').toString(16)};\n",
-    s"         claim 0x${claimAddr(i, 'M').toString(16)};\n",
-    s"        };\n") ++ (if (!supervisor) Seq() else Seq(
-    s"        s {\n",
-    s"         ie 0x${enableAddr(i, 'S').toString(16)};\n",
-    s"         thresh 0x${threshAddr(i, 'S').toString(16)};\n",
-    s"         claim 0x${claimAddr(i, 'S').toString(16)};\n",
-    s"        };\n")) ++ Seq(
-    s"      };\n")).mkString
-  }
-
   // Assign all the devices unique ranges
   lazy val sources = intnode.edgesIn.map(_.source)
   lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
@@ -146,11 +114,12 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
     // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
     val harts = io.harts.flatten
 
-    println("\nInterrupt map:")
+    println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
     flatSources.foreach { s =>
       // +1 because 0 is reserved, +1-1 because the range is half-open
       println(s"  [${s.range.start+1}, ${s.range.end}] => ${s.name}")
     }
+    println("")
 
     require (nDevices == interrupts.size)
     require (nHarts == harts.size)

src/main/scala/uncore/devices/Prci.scala

@@ -50,16 +50,6 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet
     sourceFn       = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
     sinkFn         = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
 
-  // Legacy stuff:
-  val globalConfigString = Seq(
-    s"rtc {\n",
-    s"  addr 0x${(address + timeOffset).toString(16)};\n",
-    s"};\n").mkString
-  val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
-    s"      timecmp 0x${(address + timecmpOffset(i)).toString(16)};\n",
-    s"      ipi 0x${(address + msipOffset(i)).toString(16)};\n").mkString
-  }
-
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
       val rtcTick = Bool(INPUT)

src/main/scala/uncore/tilelink2/Parameters.scala

@@ -23,8 +23,7 @@ case class TLManagerParameters(
   supportsPutPartial: TransferSizes = TransferSizes.none,
   supportsHint:       TransferSizes = TransferSizes.none,
   // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
-  fifoId:             Option[Int]   = None,
+  fifoId:             Option[Int]   = None)
-  customDTS:          Option[String]= None)
 {
   require (!address.isEmpty)
   address.foreach { a => require (a.finite) }
@@ -54,17 +53,6 @@ case class TLManagerParameters(
 
   val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
 
-  // Generate the config string (in future device tree)
-  lazy val dts = customDTS.getOrElse {
-    val header = s"${name} {\n"
-    val middle = address.map { a =>
-      require (a.contiguous) // Config String is not so flexible
-      "  addr 0x%x;\n  size 0x%x;\n".format(a.base, a.mask+1)
-    }
-    val footer = "}\n"
-    header + middle.reduce(_ + _) + footer
-  }
-
   // The device had better not support a transfer larger than it's alignment
   val minAlignment = address.map(_.alignment).min
   require (minAlignment >= maxTransfer)