riscv/rocket-chip
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build: remove the now obsolete config string

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Wesley W. Terpstra committed 2017-03-02 21:19:23 -08:00
1 parent 93ca555c20
commit d3c5318714
6 files changed
+9 -102
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src/main/scala/rocketchip/Periphery.scala
+1 -1
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@@ -305,7 +305,7 @@ trait PeripheryBootROM {
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dts)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}