riscv/rocket-chip
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build: remove the now obsolete config string

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This commit is contained in:
Wesley W. Terpstra
2017-03-02 11:02:35 -08:00
parent 93ca555c20
commit d3c5318714
6 changed files with 9 additions and 102 deletions
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2
src/main/scala/rocketchip/Periphery.scala
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@ -305,7 +305,7 @@ trait PeripheryBootROM {
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dts)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}

42
src/main/scala/rocketchip/Utils.scala
View File

@ -52,50 +52,18 @@ class GlobalVariable[T] {
def get: T = { require(assigned); variable }
}
object GenerateConfigString {
def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
val c = CoreplexParameters()(p)
val res = new StringBuilder
res append plic.globalConfigString
res append clint.globalConfigString
res append "core {\n"
c.tilesParams.zipWithIndex.map { case(t, i) =>
val isa = {
val m = if (t.core.mulDiv.nonEmpty) "m" else ""
val a = if (t.core.useAtomics) "a" else ""
val f = if (t.core.fpu.nonEmpty) "f" else ""
val d = if (t.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
val c = if (t.core.useCompressed) "c" else ""
val s = if (t.core.useVM) "s" else ""
s"rv${p(XLen)}i$m$a$f$d$c$s"
}
res append s" $i {\n"
res append " 0 {\n"
res append s" isa $isa;\n"
res append clint.hartConfigStrings(i)
res append plic.hartConfigStrings(i)
res append " };\n"
res append " };\n"
}
res append "};\n"
peripheryManagers.foreach { manager => res append manager.dts }
res append '\u0000'
res.toString
}
}
object GenerateBootROM {
def apply(p: Parameters, address: BigInt, configString: String) = {
def apply(p: Parameters, address: BigInt, dts: String) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
require(address == address.toInt)
val configStringAddr = address.toInt + rom.capacity
val dtsAddr = address.toInt + rom.capacity
require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr)
rom.array() ++ (configString.getBytes.toSeq)
"DTS address position should not be occupied by code")
rom.putInt(12, dtsAddr)
rom.array() ++ (dts.getBytes.toSeq)
}
}