riscv/rocket-chip
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change number of tlb entries

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Yunsup Lee 2012-03-16 17:08:03 -07:00
parent f0157b9e2a
commit d38603a4ee
2 changed files with 3 additions and 2 deletions
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3
rocket/src/main/scala/consts.scala
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@ -218,8 +218,9 @@ object Constants
val MEM_DATA_BITS = 128 val MEM_DATA_BITS = 128
val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
val DTLB_ENTRIES = 8; val DTLB_ENTRIES = 16
val ITLB_ENTRIES = 8; val ITLB_ENTRIES = 8;
val VITLB_ENTRIES = 4
val START_ADDR = 0x2000; val START_ADDR = 0x2000;

2
rocket/src/main/scala/cpu.scala
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@ -28,7 +28,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
val dtlb = new rocketDTLB(DTLB_ENTRIES); val dtlb = new rocketDTLB(DTLB_ENTRIES);
val itlb = new rocketITLB(ITLB_ENTRIES); val itlb = new rocketITLB(ITLB_ENTRIES);
val vitlb = new rocketITLB(ITLB_ENTRIES); val vitlb = new rocketITLB(VITLB_ENTRIES)
val ptw = new rocketPTW(); val ptw = new rocketPTW();
val arb = new rocketDmemArbiter(DCACHE_PORTS) val arb = new rocketDmemArbiter(DCACHE_PORTS)