From d38603a4ee0d5b1c3f13e814eac1035ac5fd894d Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 16 Mar 2012 17:08:03 -0700 Subject: [PATCH] change number of tlb entries --- rocket/src/main/scala/consts.scala | 3 ++- rocket/src/main/scala/cpu.scala | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index f671e29f..a5a497df 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -218,8 +218,9 @@ object Constants val MEM_DATA_BITS = 128 val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS - val DTLB_ENTRIES = 8; + val DTLB_ENTRIES = 16 val ITLB_ENTRIES = 8; + val VITLB_ENTRIES = 4 val START_ADDR = 0x2000; diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 3f902049..7acacb29 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -28,7 +28,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) val dtlb = new rocketDTLB(DTLB_ENTRIES); val itlb = new rocketITLB(ITLB_ENTRIES); - val vitlb = new rocketITLB(ITLB_ENTRIES); + val vitlb = new rocketITLB(VITLB_ENTRIES) val ptw = new rocketPTW(); val arb = new rocketDmemArbiter(DCACHE_PORTS)