riscv/rocket-chip
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Plic: remove path from ready to bits

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This commit is contained in:
Wesley W. Terpstra 2016-10-27 21:35:16 -07:00
parent 545154c1c3
commit d2e9fa8ec6
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/uncore/devices/Plic.scala
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@ -106,14 +106,14 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters {
} else (x.head, UInt(0)) } else (x.head, UInt(0))
} }
val maxDevs = Wire(Vec(cfg.nHarts, UInt(width = log2Up(pending.size)))) val maxDevs = Reg(Vec(cfg.nHarts, UInt(width = log2Up(pending.size))))
for (hart <- 0 until cfg.nHarts) { for (hart <- 0 until cfg.nHarts) {
val effectivePriority = val effectivePriority =
for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail) for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail)
yield Cat(p && en, pri) yield Cat(p && en, pri)
val (maxPri, maxDev) = findMax((UInt(1) << priority(0).getWidth) +: effectivePriority) val (maxPri, maxDev) = findMax((UInt(1) << priority(0).getWidth) +: effectivePriority)
maxDevs(hart) := Reg(next = maxDev) maxDevs(hart) := maxDev
io.harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart)) io.harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart))
} }