From d2e9fa8ec63fcc7991728037cc64404587a91714 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 27 Oct 2016 21:35:16 -0700 Subject: [PATCH] Plic: remove path from ready to bits --- src/main/scala/uncore/devices/Plic.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index 582d1131..33c7a526 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -106,14 +106,14 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters { } else (x.head, UInt(0)) } - val maxDevs = Wire(Vec(cfg.nHarts, UInt(width = log2Up(pending.size)))) + val maxDevs = Reg(Vec(cfg.nHarts, UInt(width = log2Up(pending.size)))) for (hart <- 0 until cfg.nHarts) { val effectivePriority = for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail) yield Cat(p && en, pri) val (maxPri, maxDev) = findMax((UInt(1) << priority(0).getWidth) +: effectivePriority) - maxDevs(hart) := Reg(next = maxDev) + maxDevs(hart) := maxDev io.harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart)) }