riscv/rocket-chip
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rename trc (tile reset clock) bundles to tcr (tile clock reset)

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This commit is contained in:
Yunsup Lee 2016-09-21 18:18:45 -07:00
parent 5bb575ef74
commit d2df6397cd
2 changed files with 15 additions and 15 deletions
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24
src/main/scala/coreplex/Coreplex.scala
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@ -40,7 +40,7 @@ class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
trait TileClockResetBundle { trait TileClockResetBundle {
val c: CoreplexConfig val c: CoreplexConfig
val trcs = Vec(c.nTiles, new Bundle { val tcrs = Vec(c.nTiles, new Bundle {
val clock = Clock(INPUT) val clock = Clock(INPUT)
val reset = Bool(INPUT) val reset = Bool(INPUT)
}) })
@ -51,21 +51,21 @@ trait AsyncConnection {
val tiles: Seq[Tile] val tiles: Seq[Tile]
val uncoreTileIOs: Seq[TileIO] val uncoreTileIOs: Seq[TileIO]
(tiles, uncoreTileIOs, io.trcs).zipped foreach { case (tile, uncore, trc) => (tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>
tile.clock := trc.clock tile.clock := tcr.clock
tile.reset := trc.reset tile.reset := tcr.reset
(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(trc.clock, trc.reset, t) } (uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(trc.clock, trc.reset, t) } (uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
tile.io.slave.foreach { _ <> AsyncUTileLinkTo(trc.clock, trc.reset, uncore.slave.get)} tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
val ti = tile.io.interrupts val ti = tile.io.interrupts
val ui = uncore.interrupts val ui = uncore.interrupts
ti.debug := LevelSyncTo(trc.clock, ui.debug) ti.debug := LevelSyncTo(tcr.clock, ui.debug)
ti.mtip := LevelSyncTo(trc.clock, ui.mtip) ti.mtip := LevelSyncTo(tcr.clock, ui.mtip)
ti.msip := LevelSyncTo(trc.clock, ui.msip) ti.msip := LevelSyncTo(tcr.clock, ui.msip)
ti.meip := LevelSyncTo(trc.clock, ui.meip) ti.meip := LevelSyncTo(tcr.clock, ui.meip)
ti.seip.foreach { _ := LevelSyncTo(trc.clock, ui.seip.get) } ti.seip.foreach { _ := LevelSyncTo(tcr.clock, ui.seip.get) }
tile.io.hartid := uncore.hartid tile.io.hartid := uncore.hartid
tile.io.resetVector := uncore.resetVector tile.io.resetVector := uncore.resetVector

6
src/main/scala/rocketchip/ExampleTop.scala
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@ -62,8 +62,8 @@ class ExampleMultiClockTopBundle(p: Parameters) extends ExampleTopBundle(p)
class ExampleMultiClockTopModule[+L <: ExampleMultiClockTop, +B <: ExampleMultiClockTopBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b) { class ExampleMultiClockTopModule[+L <: ExampleMultiClockTop, +B <: ExampleMultiClockTopBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b) {
val multiClockCoreplexIO = coreplexIO.asInstanceOf[MultiClockCoreplexBundle] val multiClockCoreplexIO = coreplexIO.asInstanceOf[MultiClockCoreplexBundle]
multiClockCoreplexIO.trcs foreach { trc => multiClockCoreplexIO.tcrs foreach { tcr =>
trc.clock := clock tcr.clock := clock
trc.reset := reset tcr.reset := reset
} }
} }