riscv/rocket-chip
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rename trc (tile reset clock) bundles to tcr (tile clock reset)

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This commit is contained in:
Yunsup Lee
2016-09-21 18:18:45 -07:00
parent 5bb575ef74
commit d2df6397cd
2 changed files with 15 additions and 15 deletions
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6
src/main/scala/rocketchip/ExampleTop.scala
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@ -62,8 +62,8 @@ class ExampleMultiClockTopBundle(p: Parameters) extends ExampleTopBundle(p)
class ExampleMultiClockTopModule[+L <: ExampleMultiClockTop, +B <: ExampleMultiClockTopBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b) {
val multiClockCoreplexIO = coreplexIO.asInstanceOf[MultiClockCoreplexBundle]
multiClockCoreplexIO.trcs foreach { trc =>
trc.clock := clock
trc.reset := reset
multiClockCoreplexIO.tcrs foreach { tcr =>
tcr.clock := clock
tcr.reset := reset
}
}