riscv/rocket-chip
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Don't stall the frontend, making it easier to add more features later

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Andrew Waterman
2017-04-19 16:51:39 -07:00
committed by Andrew Waterman
parent 061a0adceb
commit d24d8ff84b
4 changed files with 55 additions and 54 deletions
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2
src/main/scala/rocket/IBuf.scala
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@@ -84,7 +84,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
val ae = valid & (Mux(buf.ae, bufMask, UInt(0)) | Mux(io.imem.bits.ae, ~bufMask, UInt(0)))
val ic_replay = valid & (Mux(buf.replay, bufMask, UInt(0)) | Mux(io.imem.bits.replay, ~bufMask, UInt(0)))
val ibufBTBHitMask = Mux(ibufBTBHit, UIntToOH(ibufBTBResp.bridx), UInt(0))
assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
assert(!io.imem.valid || !io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
val icBTBHitMask = Mux(io.imem.bits.btb.valid, UIntToOH(io.imem.bits.btb.bits.bridx +& nBufValid - pcWordBits), UInt(0))
val btbHitMask = ibufBTBHitMask & bufMask | icBTBHitMask & ~bufMask