riscv/rocket-chip
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Cover all exceptions and interrupts

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This commit is contained in:
Andrew Waterman 2018-01-16 00:45:50 -08:00
parent 8799508b1f
commit d2399b6d0e
1 changed files with 16 additions and 14 deletions
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30
src/main/scala/rocket/CSR.scala
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@ -566,20 +566,22 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}
}
for (
(cover_reg, cover_reg_label) <- List(
(mCause, "MCAUSE"),
(sCause, "SCAUSE")
);
(cover_cause_code, cover_cause_label) <- List(
(Causes.user_ecall, "ECALL_USER"),
(Causes.supervisor_ecall, "ECALL_SUPERVISOR"),
(Causes.hypervisor_ecall, "ECALL_HYPERVISOR"),
(Causes.machine_ecall, "ECALL_MACHINE")
)
) {
cover((xcause_dest === cover_reg) && (cause === UInt(cover_cause_code)),
s"${cover_reg_label}_${cover_cause_label}")
for (i <- 0 until supported_interrupts.getWidth) {
val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0 && cause === (BigInt(1) << (xLen - 1)).U + i
val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0
cover(en, s"INTERRUPT_M_$i")
cover(en && delegable && delegate, s"INTERRUPT_S_$i")
}
for (i <- 0 until xLen) {
val supported_exceptions = 0x87e |
(if (usingCompressed && !coreParams.misaWritable) 0 else 1) |
(if (usingUser) 0x100 else 0) |
(if (usingVM) 0xb200 else 0)
if (((supported_exceptions >> i) & 1) != 0) {
val en = exception && cause === i
cover(en, s"EXCEPTION_M_$i")
cover(en && delegate, s"EXCEPTION_S_$i")
}
}
when (insn_ret) {